公开(公告)号：US10763213B2

公开(公告)日：2020-09-01

申请号：US16037595

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L23/535 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28 ,  H01L23/528 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11 ,  H01L29/49

Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.

公开(公告)号：US20200271716A1

公开(公告)日：2020-08-27

申请号：US16794977

申请日：2020-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas CORDIER

IPC: G01R31/28

Abstract: An electronic assembly includes a board and a system mounted to the board. The system includes an impedance matching circuit coupled to a contactless component. A detection circuit operates to carrying out a process for detecting on the board of potential faults in the system mounted to the board. The detection circuit includes a circuit incorporated into the contactless component itself and configured to carrying out a first part of the process for detecting. A processing circuit of the detection circuit performs a second part of the process for detecting based on results of the first part.

公开(公告)号：US10742145B2

公开(公告)日：2020-08-11

申请号：US16281604

申请日：2019-02-21

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gwenael Maillet ,  Jean-Louis Labyre ,  Gilles Bas

IPC: H02P7/29 ,  H02P7/00 ,  G05B19/042 ,  G06K19/07 ,  H02P7/03 ,  G06K19/00

Abstract: Control over the operation of an electrically-controlled motor is supported by an interface circuit between the electrically-controlled motor and a near-field radio frequency communication controller. The interface circuit includes a first circuit that receives at least one control set point through a near-field radio frequency communication issued by the near-field radio frequency communication controller. A second circuit of the interface generates one or more electric signals in pulse width modulation based on the control set point.

公开(公告)号：US10686046B2

公开(公告)日：2020-06-16

申请号：US16513145

申请日：2019-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Julien Delalleau

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11521 ,  G11C16/04 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11524 ,  H01L29/78 ,  H01L21/306

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20200183834A1

公开(公告)日：2020-06-11

申请号：US16691957

申请日：2019-11-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent Folliot ,  Pierre Demaj

IPC: G06F12/06 ,  G06N3/04

Abstract: A method can be used to determine an overall memory size of a global memory area to be allocated in a memory intended to store input data and output data from each layer of a neural network. An elementary memory size of an elementary memory area intended to store the input data and the output data from the layer is determined for each layer. The elementary memory size is in the range between a memory size for the input data or output data from the layer and a size equal to the sum of the memory size for the input data and the memory size for the output data from the layer. The overall memory size is determined based on the elementary memory sizes associated with the layers. The global memory area contains all the elementary memory areas.

公开(公告)号：US10679699B2

公开(公告)日：2020-06-09

申请号：US16048524

申请日：2018-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet ,  Roberto Simola

IPC: G11C16/04 ,  H01L27/11517 ,  H01L29/423

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

公开(公告)号：US20200176577A1

公开(公告)日：2020-06-04

申请号：US16783401

申请日：2020-02-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11524

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

公开(公告)号：US20200119644A1

公开(公告)日：2020-04-16

申请号：US16599450

申请日：2019-10-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sebastien ORTET ,  Didier DAVINO ,  Cedric THOMAS

IPC: H02M3/158 ,  H02M1/36

Abstract: An electronic device includes a switched-mode power supply having a first operating phase during which the output node of the switched-mode power supply is coupled by an on switch to a source of a first reference voltage. The first operating phase is followed by a second operation phase during which the output node of the switched-mode power supply is in a high impedance state. While in the second operating phase, a capacitor connected to the output node of the switched-mode power supply at least partially discharges into a load.

公开(公告)号：US10585738B2

公开(公告)日：2020-03-10

申请号：US14996107

申请日：2016-01-14

Applicant: Proton World International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Fabrice Marinet ,  Jean-Louis Modave ,  Gilles Van Assche ,  Ronny Van Keer

IPC: G06F11/00 ,  G06F11/07 ,  G06F21/55 ,  G06F21/75

Abstract: The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device.

公开(公告)号：US20200076476A1

公开(公告)日：2020-03-05

申请号：US16542747

申请日：2019-08-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Tramoni

IPC: H04B5/00 ,  H02M7/06 ,  H03K3/03

Abstract: A near-field communication device includes an oscillating circuit, a rectifying bridge configured to rectify a voltage across the oscillating circuit, and a voltage-controlled oscillator configured to supply a reference frequency. The voltage-controlled oscillator is powered and controlled by a voltage that is a function of an output voltage of the rectifying bridge.