公开(公告)号：US09577116B2

公开(公告)日：2017-02-21

申请号：US14963684

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/866 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.

Abstract translation: 本发明涉及一种齐纳二极管，其包括具有第一导电类型的阴极区，形成在具有第二导电类型的半导体衬底的表面上。 齐纳二极管包括形成在阴极区下面的具有第二导电类型的阳极区域。 一个或多个沟槽隔离将阴极和阳极区域与衬底的其余部分隔离。 第一导电区域被配置为当经受足够的电压时，产生垂直于阴极和阳极区域之间的界面的第一电场。 第二导电区域被配置为当经受足够的电压时，产生平行于阴极和阳极区域之间的界面的第二电场。

公开(公告)号：US10679699B2

公开(公告)日：2020-06-09

申请号：US16048524

申请日：2018-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet ,  Roberto Simola

IPC: G11C16/04 ,  H01L27/11517 ,  H01L29/423

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

公开(公告)号：US11031082B2

公开(公告)日：2021-06-08

申请号：US16866955

申请日：2020-05-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet ,  Roberto Simola

IPC: G11C16/04 ,  H01L27/11517 ,  H01L29/423

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

公开(公告)号：US09577053B2

公开(公告)日：2017-02-21

申请号：US14963670

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/866 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66106 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

Abstract translation: 本公开涉及一种齐纳二极管，其包括在平行于衬底表面的平面上形成在半导体衬底中的齐纳二极管结，并位于具有第一导电类型的阳极区域和具有第二导电类型的阴极区域之间 ，阴极区域从衬底的表面延伸。 第一导电区域被配置为在向第一导电区域施加第一电压时产生垂直于齐纳二极管结的平面的第一电场，并且第二导电区域被配置为沿着第一导电区域的平面生成第二电场 在向第二导电区施加第二电压时的齐纳二极管结。

公开(公告)号：US12021074B2

公开(公告)日：2024-06-25

申请号：US17516920

申请日：2021-11-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Roberto Simola

IPC: H01L29/40 ,  H01L21/70 ,  H01L27/01 ,  H10B41/41 ,  H10B41/42

CPC classification number: H01L27/016 ,  H01L21/707 ,  H10B41/41 ,  H10B41/42

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

公开(公告)号：US09954119B2

公开(公告)日：2018-04-24

申请号：US15402758

申请日：2017-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/866 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66106 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

公开(公告)号：US12004432B2

公开(公告)日：2024-06-04

申请号：US17507645

申请日：2021-10-21

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Roberto Simola ,  Yohann Moustapha-Rabault

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/231 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/882 ,  H10N70/883

Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

公开(公告)号：US20160276496A1

公开(公告)日：2016-09-22

申请号：US14963684

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/866 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.

Abstract translation: 本发明涉及一种齐纳二极管，其包括具有第一导电类型的阴极区，形成在具有第二导电类型的半导体衬底的表面上。 齐纳二极管包括形成在阴极区下面的具有第二导电类型的阳极区域。 一个或多个沟槽隔离将阴极和阳极区域与衬底的其余部分隔离。 第一导电区域被配置为当经受足够的电压时，产生垂直于阴极和阳极区域之间的界面的第一电场。 第二导电区域被配置为当经受足够的电压时，产生平行于阴极和阳极区域之间的界面的第二电场。

公开(公告)号：US20160276447A1

公开(公告)日：2016-09-22

申请号：US14963670

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/866

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66106 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

Abstract translation: 本公开涉及一种齐纳二极管，其包括在平行于衬底表面的平面上形成在半导体衬底中的齐纳二极管结，并位于具有第一导电类型的阳极区域和具有第二导电类型的阴极区域之间 ，阴极区域从衬底的表面延伸。 第一导电区域被配置为在向第一导电区域施加第一电压时产生垂直于齐纳二极管结的平面的第一电场，并且第二导电区域被配置为沿着第一导电区域的平面生成第二电场 在向第二导电区施加第二电压时的齐纳二极管结。