公开(公告)号：US08487793B2

公开(公告)日：2013-07-16

申请号：US13242675

申请日：2011-09-23

Applicant: Roger Petigny ,  Hugo Gicquel ,  Sophie Minot

Inventor： Roger Petigny ,  Hugo Gicquel ,  Sophie Minot

IPC: H03M1/06

CPC classification number: H03M1/1047 ,  H03M1/164

Abstract: Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset.

Abstract translation: 用于处理模拟信号的装置，包括具有偏移的流水线架构的模拟数字转换器，以及被配置为补偿所述偏移的补偿装置，所述补偿装置包括数字校正装置，被配置为校正基于偏移的整数部分 对由模拟数字转换器传送的数字信号和模拟数字转换器的最后级中包括的模拟校正装置进行校正，并且被配置为校正偏移的小数部分。

公开(公告)号：US08462031B2

公开(公告)日：2013-06-11

申请号：US13024729

申请日：2011-02-10

Applicant: Didier Belot ,  Jean-Baptiste Begueret ,  Yann Deval ,  Dominique Dallet ,  André Mariano

Inventor： Didier Belot ,  Jean-Baptiste Begueret ,  Yann Deval ,  Dominique Dallet ,  André Mariano

IPC: H03M3/02

CPC classification number: H03M3/458 ,  H03M3/402 ,  H03M3/484 ,  H03M3/50

Abstract: Continuous time analogue/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analogue input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).

Abstract translation: 连续时间模拟/数字转换器，包括被配置为接收模拟输入信号（x（t））并且包括其斩波频率等于采样的一半的高通滤波装置（MF）的Σ-Δ调制器（MSD1） 调制器（MSD1）的量化装置（QTZ）的频率（Fs）。

公开(公告)号：US08458638B2

公开(公告)日：2013-06-04

申请号：US13023172

申请日：2011-02-08

Applicant: Olivier Menut ,  Laurent Bergher ,  Emek Yesilada ,  Yorick Trouiller ,  Franck Foussadier ,  Raphaël Bingert

Inventor： Olivier Menut ,  Laurent Bergher ,  Emek Yesilada ,  Yorick Trouiller ,  Franck Foussadier ,  Raphaël Bingert

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  H01L27/085 ,  H01L27/11803

Abstract: A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion.

Abstract translation: 一种旨在用于形成集成电路的单元库，该库限定包括最小尺寸的第一MOS晶体管的第一单元和包括具有较低漏电流的第二MOS晶体管的第二单元，其中第二单元占用相同 表面积作为第一单元，并且第二MOS晶体管具有与第一MOS晶体管的栅极相同长度的栅极，其栅极在其中心部分至少具有第一宽度，并且在两侧的至少第二宽度上具有较大长度 的中心部分。

公开(公告)号：US08458427B2

公开(公告)日：2013-06-04

申请号：US13022099

申请日：2011-02-07

Applicant: Giuseppe Guarnaccia ,  Raffaele Guarrasi ,  Radhia Kacem

Inventor： Giuseppe Guarnaccia ,  Raffaele Guarrasi ,  Radhia Kacem

IPC: G06F12/00

CPC classification number: G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

Abstract: A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.

Abstract translation: 同步系统包括存储器和控制电路。 所述控制电路包括用于以第一时钟信号在所述存储器中写入数据的写入接口，其中所述写入接口被配置为响应写入命令与写入指针一起操作;读取接口，用于以第二时钟信号从所述存储器读取数据 时钟信号，其中所述读取接口被配置为响应于读取命令而与读取指针一起操作，用于使所述写入指针和所述读取指针与同步等待时间同步的同步电路，以及用于在存储器中用 精细延迟，其中精细延迟小于同步等待时间。

公开(公告)号：US08397360B2

公开(公告)日：2013-03-19

申请号：US12896394

申请日：2010-10-01

Applicant: Pierre Bar ,  Sylvain Joblot ,  Jean-Francois Carpentier

Inventor： Pierre Bar ,  Sylvain Joblot ,  Jean-Francois Carpentier

IPC: H01G7/00

CPC classification number: H03H3/04 ,  H03H2003/0442 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49004 ,  Y10T29/49005 ,  Y10T29/4908

Abstract: A method of adjustment on manufacturing of a monolithic oscillator including circuit elements and a BAW resonator, this method including the steps of: a) forming the circuit elements and the resonator and electrically connecting them; b) covering the resonator with a frequency adjustment layer; c) measuring the output frequency of the oscillator; d) modifying the thickness of the frequency adjustment layer to modify the output frequency of the oscillator.

Abstract translation: 一种调整制造包括电路元件和BAW谐振器的单片振荡器的方法，该方法包括以下步骤：a）形成电路元件和谐振器并将它们电连接; b）用频率调节层覆盖谐振器; c）测量振荡器的输出频率; d）修改频率调节层的厚度以修改振荡器的输出频率。

公开(公告)号：US20130026846A1

公开(公告)日：2013-01-31

申请号：US13557593

申请日：2012-07-25

Applicant: Frederic Gianesello ,  Romain Pilard ,  Cedric Durand

Inventor： Frederic Gianesello ,  Romain Pilard ,  Cedric Durand

IPC: H01F27/28 ,  H01F27/42 ,  H01F7/06 ,  H01F37/00

CPC classification number: H03H7/42 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/38 ,  H01F27/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H04W88/02 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

Abstract translation: 平衡不平衡型变压器包括初级感应电路和二次感应电路，该电感电路容纳在与次级电路的端子并联连接并与主电路和次级电路感应耦合的附加感应绕组内。

公开(公告)号：US08363106B2

公开(公告)日：2013-01-29

申请号：US12417223

申请日：2009-04-02

Applicant: Lionel Martin ,  Tony Baudon

Inventor： Lionel Martin ,  Tony Baudon

IPC: H04N7/18

CPC classification number: G08B13/19652 ,  G08B13/19602 ,  G08B13/19641

Abstract: The present disclosure relates to a video surveillance method comprising steps of a video camera periodically capturing an image of a zone to be monitored, analyzing the image to detect a presence therein, and of the video camera transmitting the image only if a presence has been detected in the image.

Abstract translation: 本公开涉及一种视频监视方法，包括以下步骤：摄像机周期性地捕获要监视的区域的图像，分析图像以检测其中的存在，以及仅在已经检测到存在的情况下发送图像的摄像机 在图像中。

公开(公告)号：US20130003255A1

公开(公告)日：2013-01-03

申请号：US13523211

申请日：2012-06-14

Applicant: Stephane Letual ,  Sarah Verhaeren

Inventor： Stephane Letual ,  Sarah Verhaeren

IPC: H01G4/012

CPC classification number: H01G4/38 ,  H01L27/0605 ,  H03M1/468

Abstract: An integrated capacitive device includes an electrically conducting comb, at least some of whose teeth form first electrodes of capacitors, and electrically conducting fingers extending between the teeth of the comb so as to form second electrodes of the capacitors. The device includes a first finger-teeth set having a single reference finger forming a reference capacitor having a reference capacitive value, at least one second finger-teeth set including several fingers, the reference finger and the number of fingers of the second finger-teeth set or sets forming a geometric series with ratio two. At least one additional set includes a single additional finger forming, with at least one tooth of the comb, an additional capacitor having an additional capacitive value substantially equal to half the reference capacitive value.

Abstract translation: 集成电容性装置包括导电梳，其至少一些齿形成电容器的第一电极，以及在梳齿之间延伸的导电指，以形成电容器的第二电极。 该装置包括具有单个参考手指的第一手指齿组合件，形成具有参考电容值的参考电容器，至少一个第二指状齿组合，其包括多个指状物，参考手指和第二指状齿的手指数 设置或设置形成具有比率2的几何系列。 至少一个附加组包括单个附加手指形成，其中梳子的至少一个齿，具有基本上等于参考电容值的一半的附加电容值的附加电容器。

公开(公告)号：US20130002366A1

公开(公告)日：2013-01-03

申请号：US13537938

申请日：2012-06-29

Applicant: Marc Sabut ,  Severin Trochut ,  Christophe Curis

Inventor： Marc Sabut ,  Severin Trochut ,  Christophe Curis

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H02M3/156

Abstract: A pulse width modulation device includes a switching transistor for defining modulation phases, a capacitor, and switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor. A constant current source is connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold.

Abstract translation: 脉冲宽度调制装置包括用于定义调制相位的开关晶体管，电容器和布置成：a）在第一相位中，将电容器充电到与开关晶体管的导通/截止阈值相对应的电压，以及b） 在第二阶段中，在用于施加设定点电压的端子和开关晶体管的栅极之间连接电容器。 连接恒流源以在电容器中施加电流，以使开关晶体管的栅极朝向导通/截止阈值。

公开(公告)号：US08344918B2

公开(公告)日：2013-01-01

申请号：US12027696

申请日：2008-02-07

Applicant: Pierre Baudin ,  Cyril Joubert

Inventor： Pierre Baudin ,  Cyril Joubert

IPC: H03M1/48

CPC classification number: H03L7/091 ,  G04F10/005

Abstract: A process inserts a random noise in a Time to Digital Converter (TDC) designed for calculating the phase error between a first high frequency signal FDCO with respect to a second reference signal, switching at a lower frequency. The process involves: processing of the first signal FDCO by using a chain of delays having a set of n elementary delays which number is chosen so as to extend over a full period of the first signal; storing the outputs of the chain of delays in a set of latches and generation of a thermometer code presenting a stream of “1” separated from a stream of “0” by a border corresponding to the transition of the first signal with respect to the second reference signal; reducing the thermometer code by a random number PN of bits; processing of the result in an edge detecting and thermometer code decoding so as to generate two variables Δtr and Δtf which are representative of the difference between the rise and fall time of the first signal with respect to the second reference signal; computing the normalized gain so as to generate an average value of 1/TDCO; adding to the value Δtr a binary value corresponding to the number of bits PN; multiplying the preceding result by the average value of 1/TDCO and computing the phase error between the signals. The delay chain may be arranged with inverters. The process is particularly but not exclusively useful for carrying out a TDC convertor for the purpose of synthesizing of frequencies.

Abstract translation: 一个过程在随时间数字转换器（TDC）中插入随机噪声，该数字转换器设计用于计算相对于第二参考信号的第一高频信号FDCO之间的相位误差，以较低频率切换。 该过程涉及：通过使用具有一组n个基本延迟的延迟链来处理第一信号FDCO，该数目被选择为在第一信号的整个周期上延伸; 将所述延迟链的输出存储在一组锁存器中，以及生成温度计代码，其呈现与0的流分离的流，所述流与相对于所述第二参考信号的所述第一信号的转变相对应的边界; 通过比特的随机数PN减少温度计代码; 处理边缘检测和温度计码解码中的结果，以便产生代表第一信号相对于第二参考信号的上升和下降时间之差的变量Dgr; tr和＆Dgr; tf; 计算归一化增益以产生1 / TDCO的平均值; 添加值Dgr; tr对应于位数PN的二进制值; 将前面的结果乘以1 / TDCO的平均值，并计算信号之间的相位误差。 延迟链可以配置有逆变器。 为了合成频率，该过程特别但非完全有用于执行TDC转换器。