公开(公告)号：US07667173B2

公开(公告)日：2010-02-23

申请号：US11655773

申请日：2007-01-19

Applicant: Pierre Caubet ,  Michael Gros-Jean

Inventor： Pierre Caubet ,  Michael Gros-Jean

IPC: H01L27/00

CPC classification number: H01L31/02162 ,  G02F1/157 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14667 ,  H01L31/02164

Abstract: An integrated circuit includes at least one photosensitive element capable of delivering an electrical signal when light of at least one wavelength of the visible spectrum reaches it, and an electrooptic system functioning as an electrochemical shutter. The electrooptic system is located in the path of at least one light ray capable of reaching the photosensitive element and possesses at least one optical property, dependent on electrochemical reaction, that can be modified by an electrical control signal. The optical property is preferably transmission.

Abstract translation: 集成电路包括至少一个能够在可见光谱的至少一个波长的光到达光的时候传递电信号的光敏元件，以及用作电化学快门的电光系统。 电光系统位于能够到达感光元件的至少一条光线的路径中，并且具有取决于电化学反应的至少一种光学性质，其可以通过电控制信号进行修改。 光学性质优选为透射性。

公开(公告)号：US20100041189A1

公开(公告)日：2010-02-18

申请号：US12559810

申请日：2009-09-15

Applicant: Markus Müller ,  Alexandre Mondot ,  Pascal Besson

Inventor： Markus Müller ,  Alexandre Mondot ,  Pascal Besson

IPC: H01L21/336

CPC classification number: H01L21/31111 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/66545

Abstract: A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the device, implanting doping ions of a first type into the first region, implanting doping ions of a second type into the second region, and etching the first and second regions for a determined duration such that the first silicon oxide layer is removed and at least a part of the second silicon oxide layer remains.

Abstract translation: 一种制造器件的方法，包括以下步骤：在器件的第一区域内形成第一氧化硅层，在器件的第二区域内形成第二氧化硅层，将第一类型的掺杂离子注入第一区域; 将第二类型的掺杂离子注入到所述第二区域中，以及蚀刻所述第一和第二区域一段确定的持续时间，以使得所述第一氧化硅层被去除并且所述第二氧化硅层的至少一部分保留。

公开(公告)号：US20100019869A1

公开(公告)日：2010-01-28

申请号：US12499653

申请日：2009-07-08

Applicant: Cédric Durand ,  Fabrice Casset

Inventor： Cédric Durand ,  Fabrice Casset

IPC: H01P7/10

CPC classification number: H03H9/02448 ,  H03H3/0076 ,  H03H9/2436 ,  H03H9/2463 ,  H03H2009/0237 ,  H03H2009/02496 ,  H03H2009/2442

Abstract: A resonator including a resonant element having a bulk and columns of a material having a Young's modulus with a temperature coefficient having a sign opposite to that of the bulk.

Abstract translation: 一种谐振器，包括具有本体的谐振元件和具有杨氏模量的材料的列，其温度系数具有与本体相反的符号。

公开(公告)号：US07649212B2

公开(公告)日：2010-01-19

申请号：US11477260

申请日：2006-06-29

Applicant: Jean-Luc Morand

Inventor： Jean-Luc Morand

IPC: H01L29/32 ,  H01L29/74

CPC classification number: H01L29/417 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/861

Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Abstract translation: 一种半导体部件，其中有源接合部基本上横跨其整个厚度垂直于半导体芯片的表面延伸。 与要连接的区域的触点由导电指状物提供，其基本上与要建立触点的整个区域交叉。

公开(公告)号：US07642579B2

公开(公告)日：2010-01-05

申请号：US11713903

申请日：2007-03-05

Applicant: Arnaud Tournier ,  François Roy

Inventor： Arnaud Tournier ,  François Roy

IPC: H01L31/062 ,  H01L21/00

CPC classification number: H01L27/14689 ,  H01L27/14601 ,  H01L27/1463 ,  H01L27/14654

Abstract: A pixel having a MOS-type transistor formed in and above a semiconductor substrate of a first doping type, a buried semiconductor layer of a second doping type being placed in the substrate under the MOS transistor and separated therefrom by a substrate portion forming a well. The buried semiconductor layer comprises a thin portion forming a pinch area placed under the transistor channel area and a thick portion placed under all or part of the source/drain areas of the transistor.

Abstract translation: 形成在第一掺杂型半导体衬底中和上方的MOS型晶体管的像素，第二掺杂类型的掩埋半导体层被放置在MOS晶体管下方的衬底中，并由形成阱的衬底部分分离。 掩埋半导体层包括形成位于晶体管沟道区域下方的夹紧区域的薄部分和放置在晶体管的源极/漏极区域全部或部分之下的厚部分。

公开(公告)号：US07624261B2

公开(公告)日：2009-11-24

申请号：US11432727

申请日：2006-05-11

Applicant: Marcus Volp

Inventor： Marcus Volp

IPC: G06F9/00 ,  G06F9/24 ,  H04N7/16

CPC classification number: G06F21/575 ,  G06F9/4405 ,  G06F15/177

Abstract: A method of secure booting of an SMP architecture apparatus provides for the formation of a secure domain comprising a first processor and a part of a shared memory, before the booting of the operating system of the first processor. The operating system of a second processor is booted only after the reciprocal authentication with the first processor and, in case of authentication, the extension of the secure domain to the second processor.

Abstract translation: 在第一处理器的操作系统引导之前，SMP架构设备的安全引导的方法提供了包括第一处理器和共享存储器的一部分的安全域的形成。 第二处理器的操作系统仅在与第一处理器的相互认证之后被引导，并且在认证的情况下，将安全域的扩展到第二处理器。

公开(公告)号：US07622752B2

公开(公告)日：2009-11-24

申请号：US11317270

申请日：2005-12-23

Applicant: Frédéric Lanois ,  Sylvain Nizou

Inventor： Frédéric Lanois ,  Sylvain Nizou

IPC: H01L31/111

CPC classification number: H01L29/8725 ,  H01L29/872

Abstract: A Schottky diode with a vertical barrier extending perpendicularly to the surface of a semiconductor chip having a vertical central metal conductor in contact on the one hand with the substrate of the semiconductor chip with an interposed interface forming a Schottky barrier, and on the other hand with radially-extending conductive fingers.

Abstract translation: 肖特基二极管具有垂直于垂直于半导体芯片的表面延伸的垂直屏障，该半导体芯片的垂直中心金属导体一方面与半导体芯片的衬底接触形成肖特基势垒，另一方面与 径向延伸的导电指状物。

公开(公告)号：US07616830B2

公开(公告)日：2009-11-10

申请号：US11320165

申请日：2005-12-28

Applicant: Fritz Lebowsky ,  Marina Nicolas

Inventor： Fritz Lebowsky ,  Marina Nicolas

IPC: G06K9/40 ,  H04N5/00

CPC classification number: G06T5/002 ,  G06T2207/10016 ,  H04N19/117 ,  H04N19/119 ,  H04N19/14 ,  H04N19/186 ,  H04N19/42 ,  H04N19/86

Abstract: Artifacts of an incident digital image including pixels carrying information are reduced by determining, for certain pixels being considered from the image, displaced pixels. A displaced pixel associated with a pixel being considered is situated at a location that is displaced with respect to the location of the pixel being considered. Substitution information is determined by taking into account the variations between each piece of information carried by pixels situated at locations adjacent to the pixel being considered. The pixel being considered is then selectively replaced by a substitution pixel equal to the displaced pixel or to a combination of the displaced pixel and the pixel being considered, depending on the value of the substitution information.

Abstract translation: 包括携带信息的像素的入射数字图像的伪像通过对于从图像考虑的某些像素确定位移像素来减少。 与被考虑的像素相关联的位移像素位于相对于所考虑的像素的位置移位的位置处。 通过考虑由位于与被考虑的像素相邻的位置处的像素承载的每条信息之间的变化来确定替换信息。 根据取代信息的值，被考虑的像素被选择性地替换为等于被移位的像素的替代像素，或被替换为所考虑的位移像素和像素的组合。

公开(公告)号：US07615455B2

公开(公告)日：2009-11-10

申请号：US11523770

申请日：2006-09-19

Applicant: Pascal Chevalier ,  Alain Chantre

Inventor： Pascal Chevalier ,  Alain Chantre

IPC: H01L21/331 ,  H01L27/082

CPC classification number: H01L29/66242 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor having a base region resting by its lower surface on a collector region and surrounded with a first insulating layer, a base contact conductive region in contact with an external upper peripheral region of the base region, a second insulating region in contact with an intermediary upper peripheral region of the base region, an emitter region in contact with the central portion of the base region. The level of the central portion is higher than the level of the intermediary portion.

Abstract translation: 一种双极晶体管，具有由集电极区域的下表面固定并被第一绝缘层包围的基极区域，与基极区域的外部上部周边区域接触的基极接触导电区域，与第一绝缘区域接触的第二绝缘区域 基极区域的中间上部周边区域，与基极区域的中心部分接触的发射极区域。 中央部分的高度高于中间部分的高度。

公开(公告)号：US07612547B2

公开(公告)日：2009-11-03

申请号：US11621488

申请日：2007-01-09

Applicant: Claude Renous

Inventor： Claude Renous

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: A voltage regulation circuit intended to generate a regulated voltage for an electronic device, comprising: a transconductance amplifier based on a pair of MOS type differential amplifiers, said amplifier having a first input onto which a reference potential is applied and a second input onto which a counter reaction of said regulated voltage is input; a follower stage connected to the output from said transconductance amplifier; a MOS type transistor that will be used to make the output stage of the regulation circuit with a source connected to a first power supply potential. The transconductance amplifier comprises a resistive load 360 with a profile in K/gm, where gm is the transconductance coefficient of said input differential pair, said resistive load being connected to said first power supply potential.

Abstract translation: 一种旨在为电子设备产生调节电压的电压调节电路，包括：基于一对MOS型差分放大器的跨导放大器，所述放大器具有施加基准电位的第一输入端和第二输入端， 输入所述调节电压的反作用; 连接到所述跨导放大器的输出的跟随器级; 将用于使源极连接到第一电源电位的调节电路的输出级的MOS型晶体管。 跨导放大器包括具有K / gm的轮廓的电阻负载360，其中gm是所述输入差分对的跨导系数，所述电阻负载连接到所述第一电源电位。