公开(公告)号：US20240322814A1

公开(公告)日：2024-09-26

申请号：US18604239

申请日：2024-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Francesco PULVIRENTI ,  Salvatore Giuseppe PRIVITERA ,  Cesare BIMBI

IPC: H03K17/16 ,  H03K17/10 ,  H03K17/687

CPC classification number: H03K17/162 ,  H03K17/102 ,  H03K17/6872

Abstract: A buffer circuit for driving a GaN power switch includes an input node to receive an input signal and an output node to produce a gate signal for the GaN power switch. The buffer includes a push-pull stage that includes a first transistor coupled between a supply voltage node and the output node, a second transistor coupled between the supply voltage node and the output node, a third transistor coupled between the output node and a reference voltage node, and a fourth transistor coupled between the output node and the reference voltage node. The buffer includes a pre-buffer stage configured to receive the input signal and to produce respective driving signals for the first, second, third and fourth transistors to produce the gate signal at the output node in four consecutive phases.

公开(公告)号：US20240320359A1

公开(公告)日：2024-09-26

申请号：US18614171

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Loic Pallardy

IPC: G06F21/62 ,  G06F9/50

CPC classification number: G06F21/6218 ,  G06F9/5044

Abstract: A system-on-a-chip includes at least one slave resource, a resource isolation system, and a countermeasure circuit capable of and intended to limit the operation of the system against potential anomalies, and, for the at least one slave resource, a protection circuit configured to block or transmit transactions addressed to the resource depending on access rights of the resource and of the transaction. The protection circuit is configured to generate and directly communicate an alert signal to the countermeasure circuit in the event of a transaction being blocked.

公开(公告)号：US20240320074A1

公开(公告)日：2024-09-26

申请号：US18612406

申请日：2024-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Michael PEETERS

IPC: G06F11/07 ,  H04L9/30

CPC classification number: G06F11/0751 ,  H04L9/304 ,  H04L9/3066

Abstract: The present description concerns a method of checking a first data element, executed by an electronic device comprising a processor and a memory, wherein the first data element is divided in N second data elements being stored in the memory, and first data element being equal to the sum, modulo the dimension of a space comprising the first data element, of the N second data elements, wherein an image of the first data element by a LCG function is stored in the memory, and the method comprising a step of checking if the image of the first data element by the LCG function is equal to the sum, modulo the module of the LCG function, of a product of an integer varying from 0 to N−1 and an image of the dimension by the LCG function, and of the images of the second data elements by the LCG function.

公开(公告)号：US20240319270A1

公开(公告)日：2024-09-26

申请号：US18612251

申请日：2024-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Shikhar MAKKAR

IPC: G01R31/3177

CPC classification number: G01R31/3177

Abstract: A system for performing scan testing on a device core uses a test access port (TAP). The TAP includes a test clock (TCK) pin, a test data in (TDI) pin, and a test mode select (TMS) pin, along with a test control register (TCR) associated with it. The TCR is used to set a scan mode signal, which configures the scan flip flops within the device core for scan testing and performs the scan testing on the device core. The TCR can also be reset to exit the scan testing, with the reset being triggered by a reset circuit receiving the deassertion of both a scan enable (SE) signal and a scan input (SI) signal during the capture-phase of scan testing.

公开(公告)号：US20240305203A1

公开(公告)日：2024-09-12

申请号：US18591480

申请日：2024-02-29

Applicant: STMicroelectronics International N.V.

Inventor： Lionel ESTEVE ,  Loic BOURGUINE

IPC: H02M3/335 ,  H01L29/20 ,  H01L29/778 ,  H01L29/866 ,  H02M1/08

CPC classification number: H02M3/33515 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/866 ,  H02M1/08 ,  H02M3/33523

Abstract: The present disclosure relates to a pulse width modulation circuit of a switched-mode power supply formed in and on a monolithic semiconductor substrate with a face coated with a gallium nitride layer, said circuit being adapted to control a power transistor of said switched-mode power supply.

公开(公告)号：US20240304711A1

公开(公告)日：2024-09-12

申请号：US18592816

申请日：2024-03-01

Applicant: STMicroelectronics International N.V.

Inventor： Cristina TRINGALI ,  Aurore CONSTANT ,  Maria Eloisa CASTAGNA ,  Ferdinando IUCOLANO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462

Abstract: A HEMT transistor is formed on a semiconductor body having a semiconductive heterostructure. A gate region of a semiconductor material, is arranged on the semiconductor body and has lateral sides. Sealing regions of non-conductive material extend on the lateral sides of the gate region; and a passivation layer of non-conductive material has surface portions extending on the semiconductor body, on both sides of the gate region and at a distance therefrom. The sealing regions and the passivation regions have different characteristic, such as are of different material or have different thicknesses.

公开(公告)号：US20240304710A1

公开(公告)日：2024-09-12

申请号：US18591541

申请日：2024-02-29

Applicant: STMicroelectronics International N.V.

Inventor： Cristina TRINGALI ,  Aurore CONSTANT ,  Maria Eloisa CASTAGNA ,  Ferdinando IUCOLANO

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L29/0603 ,  H01L29/402 ,  H01L29/66431 ,  H01L29/66462

Abstract: A HEMT transistor has a body having a top surface and a heterostructure, and a gate region having a semiconductor material and arranged on the top surface of the body. The gate region has a first lateral sidewall and a second lateral sidewall opposite to the first lateral sidewall. The HEMT device further has a sealing layer of non-conductive material that extends on and in contact with the first and the second lateral sidewalls of the gate region; and a passivation layer of non-conductive material that has a surface portion. The surface portion extends on the top surface of the body, laterally to the first lateral sidewall of the gate region. The sealing layer and the passivation layer have different geometrical parameters and/or are of different material.

公开(公告)号：US12087368B2

公开(公告)日：2024-09-10

申请号：US17548096

申请日：2021-12-10

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Arpit Vijayvergia ,  Vikas Rana

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/28 ,  G11C16/0458 ,  G11C16/24

Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

公开(公告)号：US12086568B2

公开(公告)日：2024-09-10

申请号：US18134737

申请日：2023-04-14

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: G06F7/544 ,  G06F7/548 ,  H03K3/037 ,  H03K5/01 ,  H03K5/00

CPC classification number: G06F7/548 ,  G06F7/5443 ,  H03K3/037 ,  H03K5/01 ,  H03K2005/00078

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.

公开(公告)号：US20240295454A1

公开(公告)日：2024-09-05

申请号：US18117070

申请日：2023-03-03

Applicant: STMicroelectronics International N.V.

Inventor： Lorenzo BALDO ,  Filippo DANIELE ,  Enri DUQI

IPC: G01L9/12

CPC classification number: G01L9/12

Abstract: A pressure-sensor includes a substrate with a cavity therein and a membrane suspended over the cavity. The cavity is connected to external air pressure so a change in external air pressure causes out-of-plane movement of the membrane. A frame suspended over the membrane includes a segment connected to the membrane but disconnected from other frame portions. A projection extends from the frame. A first spring is connected to the projection, a second spring is connected to the segment, and an end portion connects the springs so out-of-plane movement of the membrane applies out-of-plane force to the second spring, which is transferred to the first spring by the end portion and translated to an in-plane force by the first spring and applied to the projection. This causes lateral sliding movement of the frame with respect to the substrate. A capacitive-sensor detects sliding movement of the frame with respect to the substrate.