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41.
公开(公告)号:US12021551B2
公开(公告)日:2024-06-25
申请号:US17133609
申请日:2020-12-23
申请人: Intel Corporation
发明人: James Guilford , Vinodh Gopal , Daniel Cutter , Kirk Yap
CPC分类号: H03M7/40 , G06F3/0608 , G06F3/0638 , G06F3/0673 , G11C15/00 , H03M7/3086
摘要: Apparatus and method for efficient compression block decoding using content-addressable structure for header processing. For example, one embodiment of an apparatus comprises: a header parser to extract a sequence of tokens and corresponding length values from a header of a compression block, the tokens and corresponding length values associated with a type of compression used to compress a payload of the compression block; and a content-addressable data structure builder to construct a content-addressable data structure based on the tokens and length values, the content-addressable data structure builder to write an entry in the content-addressable data structure comprising a length value and a count value, the count value indicating a number of times the length value was previously written to an entry in the content-addressable data structure.
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公开(公告)号:US12020144B2
公开(公告)日:2024-06-25
申请号:US16579765
申请日:2019-09-23
申请人: Intel Corporation
发明人: Dmitri Nikonov , Ian Young
摘要: A neural network scheme is described that uses unsupervised learning in oscillator neural networks. Training occurs by varying the weights in proportion to the output from a frequency detector. Inputs and initial weights are split into plurality of inputs and plurality of weights. These split inputs and weights can be analog or digital. Oscillators generate signals having frequencies that represent difference in inputs, initial weights, and adjusted factors. Frequency detectors are used to compare the oscillator frequencies with a synchronized frequency of all oscillators. The output of the frequency detectors are used to generate the adjusted factors, and in turn generate trained weights.
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43.
公开(公告)号:US12020028B2
公开(公告)日:2024-06-25
申请号:US17134373
申请日:2020-12-26
申请人: Intel Corporation
发明人: Naveen Mellempudi , Alexander F. Heinecke , Robert Valentine , Mark J. Charney , Christopher J. Hughes , Evangelos Georganas , Zeev Sperber , Amit Gradstein , Simon Rubanovich
CPC分类号: G06F9/30036 , G06F7/49915 , G06F9/30196 , G06F9/3887
摘要: Systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. A processor embodiment includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a destination matrix having single-precision elements, a first source matrix, and a second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values, a multiplication of different pairs of converted single-precision values to generate plurality of results, and an accumulation of the results with previous contents of a corresponding element of the destination matrix, decode circuitry to decode the fetched instruction, and the execution circuitry to respond to the decoded instruction as specified by the opcode.
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44.
公开(公告)号:US12009747B2
公开(公告)日:2024-06-11
申请号:US17133442
申请日:2020-12-23
申请人: Intel Corporation
发明人: Tarakesava Reddy Koki , Vinaya Kumar Chandrasekhara , Aiswarya Pious , Nirmala Bailur , Jagadish Vasudeva Singh
CPC分类号: H02M3/158 , G06F1/28 , H02J7/0068 , H02M1/088
摘要: Techniques and mechanisms for determining a delivery of power by a programmable power supply. In an embodiment, controller circuitry of a platform receives an indication that a load of the platform is to transition to a particular operational mode. Based on a power requirement of the operational mode, the controller circuitry identifies a mode of voltage regulation which is to be provided with converter circuitry of the platform. The controller circuitry signals that a programmable power supply, which is coupled to the platform, is to output a supply voltage at a level which is based on an amount of power loss associated with the mode of voltage regulation. In another embodiment, the controller circuitry identifies the mode of voltage regulation based on an amount of charge which is currently stored by a battery of the platform.
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45.
公开(公告)号:US12008367B2
公开(公告)日:2024-06-11
申请号:US17845103
申请日:2022-06-21
申请人: Intel Corporation
发明人: Alexander F. Heinecke , Robert Valentine , Mark J. Charney , Raanan Sade , Menachem Adelman , Zeev Sperber , Amit Gradstein , Simon Rubanovich
CPC分类号: G06F9/30036 , G06F9/3001 , G06F9/30014 , G06F9/3016 , G06F9/3802
摘要: Disclosed embodiments relate to systems and methods for performing 16-bit floating-point vector dot product instructions. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply N pairs of 16-bit floating-point formatted elements of the specified first and second sources, and accumulate the resulting products with previous contents of a corresponding single-precision element of the specified destination, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.
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公开(公告)号:US12007877B1
公开(公告)日:2024-06-11
申请号:US17708269
申请日:2022-03-30
CPC分类号: G06F11/3664 , G06F11/3688
摘要: Techniques for providing a visual code review editor are described. An electronic device is caused to display a graphical user interface including an editor portion to edit code review rules used by a code review service of a cloud provider network. The editor portion of the graphical user interface is caused to display a first graph associated with a first code review rule, the first graph including a first node, a second node, and a first edge connecting the first node and the second node. An indication that a third node has been added to the graph via the editor portion of the graphical user interface is received. The first code review rule is updated by the code review service to reflect the addition of the third node, the first code review rule is in a text format.
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公开(公告)号:US12003602B2
公开(公告)日:2024-06-04
申请号:US18060528
申请日:2022-11-30
申请人: Salesforce, Inc.
发明人: Scott Glaser , Abhinav Bagul , Kerry Fleming , Matthew R. Kunkel , Derek Spiner
IPC分类号: H04L67/566 , H04L9/40 , H04L67/561 , H04L67/564
CPC分类号: H04L67/566 , H04L63/10 , H04L63/168 , H04L67/561 , H04L67/564
摘要: A method for providing interoperability between a plurality of security services and target applications by an interoperability service. The method includes receiving a request from one of the plurality of security services to perform a task on a target application, preparing a unified data model for interaction with the target application, determining and organizing data connections to perform the task on the target application, generating a set of requests using the unified data model based on the task and utilizing business logic of the interoperability service for the data connections with the target application, transforming the set of requests into commands and data structures specific to the target application, and sending the set of requests on respective data connections with the target application.
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公开(公告)号:US12002145B2
公开(公告)日:2024-06-04
申请号:US17133573
申请日:2020-12-23
申请人: Intel Corpoation
发明人: Sven Woop , Michael J. Doyle , Sreenivas Kothandaraman , Karthik Vaidyanathan , Abhishek R. Appu , Carsten Benthin , Prasoonkumar Surti , Holger Gruen , Stephen Junkins , Adam Lake , Bret G. Alfieri , Gabor Liktor , Joshua Barczak , Won-Jong Lee
CPC分类号: G06T15/06 , G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/21
摘要: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.
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公开(公告)号:USD1027844S1
公开(公告)日:2024-05-21
申请号:US29825364
申请日:2022-01-31
申请人: ChargePoint, Inc.
设计人: Justin D. Cumming , Peter H. Muller , David Hoenig , Pasquale Romano , Darren Chin-Ho Kim , Benjamin Bylenok , Dennis Michael Heleine , Stephen Eric Sidle , Michal Lekszycki , Aaron Dayton Little , Jacky S. Wong
摘要: FIG. 1 shows a front perspective view of an electric vehicle charging station showing the claimed design;
FIG. 2 shows a front view thereof;
FIG. 3 shows a back view thereof;
FIG. 4 shows a right view thereof;
FIG. 5 shows a left view thereof;
FIG. 6 shows a top view thereof;
FIG. 7 shows a bottom view thereof; and,
FIG. 8 shows a rear perspective view thereof.
The broken lines illustrate portions of the electric vehicle charging station that form no part of the claimed design.-
公开(公告)号:USD1027841S1
公开(公告)日:2024-05-21
申请号:US29825348
申请日:2022-01-31
申请人: ChargePoint, Inc.
设计人: Justin D. Cumming , Peter H. Muller , David Hoenig , Pasquale Romano , Darren Chin-Ho Kim , Benjamin Bylenok , Dennis Michael Heleine , Stephen Eric Sidle , Michal Lekszycki , Aaron Dayton Little , Jacky S. Wong
摘要: FIG. 1 shows a front perspective view of an electric vehicle charging station showing the claimed design;
FIG. 2 shows a front view thereof;
FIG. 3 shows a back view thereof;
FIG. 4 shows a right view thereof;
FIG. 5 shows a left view thereof;
FIG. 6 shows a top view thereof;
FIG. 7 shows a bottom view thereof; and,
FIG. 8 shows a rear perspective view thereof.
The broken lines illustrate portions of the electric vehicle charging station that form no part of the claimed design.
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