公开(公告)号：US20120033522A1

公开(公告)日：2012-02-09

申请号：US12852759

申请日：2010-08-09

Applicant: Ching-Te Chuang ,  Yi-Wei Lin ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Yi-Wei Lin ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Abstract translation: 提供随机存取存储器（RAM）。 RAM包括多个字线驱动器，至少第一跟踪晶体管和第二跟踪晶体管。 每个字线驱动器具有接收解码信号的输入节点，接收操作电压的功率节点和驱动字线的驱动节点。 在一个实施例中，第一跟踪晶体管具有分别耦合到字线驱动器之一的驱动节点和第二跟踪晶体管的通道终端节点的两个通道终端节点; 其中所述第一跟踪晶体管具有跟踪字线驱动器的驱动晶体管的电子特性的电子特性，并且所述第二跟踪晶体管具有跟踪所述RAM的每个单元中的栅极晶体管的电子特性。

公开(公告)号：US20080144362A1

公开(公告)日：2008-06-19

申请号：US12040966

申请日：2008-03-03

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/412

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

Abstract translation: 为非对称SRAM单元提供技术，例如可通过提供改进的读取稳定性和改进的写入性能和余量来提供一个或多个。 第一反相器和第二反相器被交叉耦合并且被配置为在读和写字线的控制下选择性地耦合到真和互补的位线。 第一反相器由第一n型FET（NFET）和第二p型FET（PFET）形成。 可以采用过程和/或技术方法来调整FET的相对强度，以获得例如读取余量，写入裕度和/或写入性能改进。

公开(公告)号：US20080084733A1

公开(公告)日：2008-04-10

申请号：US11933505

申请日：2007-11-01

Applicant: Ching-Te Chuang ,  Jac-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jac-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

Abstract translation: 为非对称存储单元中的背栅极控制提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

公开(公告)号：US20070040584A1

公开(公告)日：2007-02-22

申请号：US11204401

申请日：2005-08-16

Applicant: Hung Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

Inventor： Hung Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

IPC: H03K19/096

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

公开(公告)号：US20070018248A1

公开(公告)日：2007-01-25

申请号：US11184244

申请日：2005-07-19

Applicant: Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo ,  Jeffrey Sleight

Inventor： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo ,  Jeffrey Sleight

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092

Abstract: Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or footers are made of bulk epitaxial CMOS devices, with or without an adaptive well-biasing scheme. The logic transistors are based on (100) SOI devices or super HOT, the header devices are in bulk (100) or (110) pFETs with or without an adaptive well biasing scheme, and the footer devices are in bulk (100) NFET with or without an adaptive well biasing scheme.

Abstract translation: 公开了一种多阈值CMOS电路和一种设计这种电路的方法。 优选实施例组合MTCMOS方案和混合SOI外延CMOS结构。 通常，逻辑晶体管（nFET和pFET都）放置在SOI中，优选地以高性能，高密度的UTSOI; 而集管或页脚由大量外延CMOS器件制成，具有或不具有自适应阱偏置方案。 逻辑晶体管基于（100）SOI器件或超级HOT，头部器件处于具有或不具有自适应阱偏置方案的体（100）或（110）pFET中，并且脚踏器件处于本体（100）NFET中 或没有自适应井偏置方案。

公开(公告)号：US20130223136A1

公开(公告)日：2013-08-29

申请号：US13484497

申请日：2012-05-31

Applicant: Ching-Te CHUANG ,  Shyh-Jye Jou ,  Wei Hwang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Hao-I Yang ,  Ming-Hsien Tu ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee

Inventor： Ching-Te CHUANG ,  Shyh-Jye Jou ,  Wei Hwang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Hao-I Yang ,  Ming-Hsien Tu ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee

IPC: G11C11/40

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/5002

Abstract: The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.

Abstract translation: 本发明提供一种包括第一反相器，第二反相器，第一通过栅极晶体管和第二通过栅极晶体管的6T SRAM。 第一反相器zs是第一上拉晶体管和第一下拉晶体管。 第二反相器包括第二上拉晶体管和第二下拉晶体管。 第二上拉晶体管的栅极与第二下拉晶体管的栅极耦合，并且第二上拉晶体管的漏极与第二下拉晶体管的漏极耦合。 SRAM可以通过控制第一位线，第二位线，GND，第一字线和电压源来测量跳闸电压，读取干扰电压和写入裕度，而不改变SRAM的物理参数 。

公开(公告)号：US20120087196A1

公开(公告)日：2012-04-12

申请号：US13075682

申请日：2011-03-30

Applicant: Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

Inventor： Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

IPC: G11C5/14

CPC classification number: G11C11/417

Abstract: The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

Abstract translation: 本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。 具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。 具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。 本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

公开(公告)号：US07973564B1

公开(公告)日：2011-07-05

申请号：US12874584

申请日：2010-09-02

Applicant: Ching-Te Chuang ,  Chien-Yu Lu

Inventor： Ching-Te Chuang ,  Chien-Yu Lu

IPC: H03K19/094

CPC classification number: H03K17/04123

Abstract: A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effect transistor (FET), a second P-type FET, a first N-type FET, and a third N-type FET. A push-up circuit is composed of these transistors and a second N-type FET and coupled to a P-type push-up FET. A load is coupled to a high voltage through the P-type push-up FET. When the digital voltage rises from a low level to a high level, the push-up circuit utilizes the original voltage drop of the capacitor to control the P-type push-up FET, whereby the gate voltage of the P-type push-up FET is at a low stabilization voltage that is lower than the ground potential. Then, the load is driven rapidly.

Abstract translation: 公开了一种高负载驱动装置。 驱动装置包括接收数字电压的逆变器。 逆变器反转数字电压，然后发出。 反相器的输出端子耦合到电容器，第一P型场效应晶体管（FET），第二P型FET，第一N型FET和第三N型FET。 上推电路由这些晶体管和第二N型FET组成并耦合到P型上推FET。 负载通过P型上推FET耦合到高电压。 当数字电压从低电平上升到高电平时，上推电路利用电容器的原始电压降来控制P型上推FET，由此P型上推电压的栅极电压 FET处于低于地电位的低稳定电压。 然后，负载被快速驱动。

公开(公告)号：US20110128796A1

公开(公告)日：2011-06-02

申请号：US12772238

申请日：2010-05-03

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C11/412

Abstract: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

Abstract translation: 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

公开(公告)号：US07903450B2

公开(公告)日：2011-03-08

申请号：US12040966

申请日：2008-03-03

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: Asymmetrical SRAM cells are improved by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

Abstract translation: 通过提供改进的读取稳定性和改进的写入性能和余量的一个或多个来改进非对称SRAM单元。 第一反相器和第二反相器被交叉耦合并且被配置为在读和写字线的控制下选择性地耦合到真和互补的位线。 第一反相器由第一n型FET（NFET）和第二p型FET（PFET）形成。 可以采用过程和/或技术方法来调整FET的相对强度，以获得例如读取余量，写入裕度和/或写入性能改进。