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公开(公告)号：US20160119710A1
公开(公告)日：2016-04-28
申请号：US14920791
申请日：2015-10-22
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson , Dustin Dale Forman , Robert Lynn Blair , Peter John Frith
IPC: H04R1/10
CPC classification number: H04R1/1041 , H04M1/6058 , H04R5/04 , H04R2420/09
Abstract: An apparatus is disclosed for inputting digital data on the output channel(s) of an audio subsystem in an audio device, without interfering with normal operation of the audio subsystem. The described circuit includes a resistive element in parallel with the expected load device, such as a headphone or speaker. The resistive element receives a modulated digital signal from a data source or a switch, and the instantaneous current through the resistive element due to the modulated digital signal is reflected in a current feedback mechanism of the audio subsystem. Demodulation logic retrieves the digital signal from the current measured by the current feedback mechanism. A capacitor is provided to prevent the current in the resistive element from the digital signal from impacting the average DC current that the feedback mechanism uses to evaluate the load device.
Abstract translation: 公开了一种用于在音频设备中的音频子系统的输出通道上输入数字数据而不干扰音频子系统的正常操作的装置。 所描述的电路包括与期望的负载装置（例如耳机或扬声器）并联的电阻元件。 电阻元件从数据源或开关接收调制的数字信号，并且由于调制的数字信号引起的通过电阻元件的瞬时电流被反映在音频子系统的电流反馈机制中。 解调逻辑从当前反馈机制测量的电流中检索数字信号。 提供电容器以防止电阻元件中的电流数字信号影响反馈机构用于评估负载装置的平均DC电流。
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42.发明授权公开(公告)号：US09098663B2
公开(公告)日：2015-08-04
申请号：US14446780
申请日：2014-07-30
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson
IPC: G06F17/50
CPC classification number: G06F17/5045 , G06F17/5063 , G06F2217/02 , G06F2217/06
Abstract: A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve an arbitrary compound value is disclosed. A recursive algorithm successively adds one or more similar nominal two-terminal elements to generate a series and/or parallel compound combination of nominal elements, the compound combination having a desired impedance. The compound value, and thus the ratio between two compound values, can be determined to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the compound value, and the ratio between values, depends primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process.
Abstract translation: 公开了一种用于产生和匹配名义上相同的初始元素以实现任意化合物值的复杂串联和/或并联组合的方法和系统。 递归算法连续地添加一个或多个相似的标称两端元件以产生具有期望阻抗的复合组合的标称元件的串联和/或并联复合组合。 可以将化合物值以及因此两个化合物值之间的比率确定为几乎任何所需的准确度，其中潜在误差比在不同值的各个元素的构造中典型地降低。 由于初始元素名义上相同，所以化合物值和值之间的比例主要取决于初始元素的连接而不是其几何形状，并且因此保持实质上恒定，而与制造过程中的变化无关。
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公开(公告)号：US08937991B2
公开(公告)日：2015-01-20
申请号：US14055785
申请日：2013-10-16
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson
CPC classification number: H04L25/4902 , H03H17/0213 , H03H17/06
Abstract: A system and method for filtering an analog signal with a finite impulse response (FIR) filter that does not require analog delay elements are disclosed. An analog signal is pulse-width encoded, and the pulse-width encoded signal passed to a delay line comprising unclocked delay elements, such as logic gates, rather than clocked delay elements such as are used in conventional FIR filters. The propagation of the input signal is thus due only to the delay inherent in each gate, and occurs based upon when a signal reaches the gate rather than being caused by a clock signal. As with a conventional FIR filter, weighting elements having impedance are used to weigh the output of each delay element, and the resulting outputs summed to obtain a filtered output signal. For certain signals, such a circuit and method provides a simpler way of filtering than conventional filters.
Abstract translation: 公开了一种使用不需要模拟延迟元件的有限脉冲响应（FIR）滤波器对模拟信号进行滤波的系统和方法。 模拟信号被脉冲宽度编码，并且脉冲宽度编码信号传递到包括诸如逻辑门之类的非锁定延迟元件的延迟线，而不是例如在常规FIR滤波器中使用的定时延迟元件。 因此，输入信号的传播仅由于每个栅极固有的延迟而发生，并且基于何时信号到达门而不是由时钟信号引起。 与常规FIR滤波器一样，具有阻抗的加权元件用于称量每个延迟元件的输出，并且所得到的输出相加以获得经滤波的输出信号。 对于某些信号，这种电路和方法提供比常规滤波器更简单的滤波方式。
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公开(公告)号：US08698660B2
公开(公告)日：2014-04-15
申请号：US13665801
申请日：2012-10-31
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson , Dustin Dale Forman
IPC: H03M3/00
Abstract: The present application describes an apparatus and method for improving the performance of ΣΔ modulators functioning as ADCs. In one embodiment, the ΣΔ modulator comprises a plurality of quantizers operating in a round-robin fashion, rather than the single quantizer of the prior art. The use of multiple quantizers allows the ΣΔ modulator to appear to be functioning at a significantly higher rate than a single quantizer allows. In another embodiment, a second-order ΣΔ modulator contains a plurality of control loops, rather than the single control loop of the prior art. The use of multiple control loops allows the ΣΔ modulator to have multiple points of maximum signal-to-noise ratio rather than a single such point as in prior art ΣΔ modulators.
Abstract translation: 本申请描述了一种用于提高＆Sgr＆amp; Dgr的性能的装置和方法; 作为ADC的调制器。 在一个实施例中，＆S＆amp; 调制器包括以循环方式操作的多个量化器，而不是现有技术的单个量化器。 使用多个量化器允许＆Sgr;＆Dgr; 调制器似乎以比单个量化器更高的速率运行。 在另一个实施例中，二阶＆S＆amp; 调制器包含多个控制回路，而不是现有技术的单个控制回路。 使用多个控制循环允许＆Sgr;＆Dgr; 调制器具有多个最大信噪比的点，而不是现有技术中的单个点;＆Dgr; 调制器
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公开(公告)号：US20130106486A1
公开(公告)日：2013-05-02
申请号：US13665801
申请日：2012-10-31
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson , Dustin Dale Forman
Abstract: The present application describes an apparatus and method for improving the performance of ΣΔ modulators functioning as ADCs. In one embodiment, the ΣΔ modulator comprises a plurality of quantizers operating in a round-robin fashion, rather than the single quantizer of the prior art. The use of multiple quantizers allows the ΣΔ modulator to appear to be functioning at a significantly higher rate than a single quantizer allows. In another embodiment, a second-order ΣΔ modulator contains a plurality of control loops, rather than the single control loop of the prior art. The use of multiple control loops allows the ΣΔ modulator to have multiple points of maximum signal-to-noise ratio rather than a single such point as in prior art ΣΔ modulators.
Abstract translation: 本申请描述了用于改善用作ADC的SigmaDelta调制器的性能的装置和方法。 在一个实施例中，SigmaDelta调制器包括以循环方式操作的多个量化器，而不是现有技术的单个量化器。 使用多个量化器可以使SigmaDelta调制器以比单个量化器允许的更高的速率运行。 在另一个实施例中，二阶SigmaDelta调制器包含多个控制回路，而不是现有技术的单个控制回路。 使用多个控制回路允许SigmaDelta调制器具有多个最大信噪比的点，而不是像现有技术的SigmaDelta调制器中的单个点。
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Patent Agency Ranking
公开(公告)号：US20040145421A1
公开(公告)日：2004-07-29
申请号：US10351266
申请日：2003-01-23
Applicant: ESS Technology, Inc.
Inventor： Andrew Martin Mallinson
IPC: H03L007/00
CPC classification number: H03L7/1806 , H03L7/18
Abstract: The invention provides a frequency locked loop and related method that enables the conversion of a signal frequency with improved stability. A frequency locked loop embodying the invention includes an input for receiving an input signal and an output for outputting an output signal having a different frequency than the input. A frequency detector is configured to receive the first factored input from the primary channel and the second factored input from the secondary channel, to calculate the difference between the first factored input and the second factored input and to produce an output based on the difference between the two factored inputs. A voltage controlled oscillator is configured to receive the output from the frequency detector, and to produce an output signal. The voltage controlled oscillator ultimately sets the output frequency based on the output of frequency detector. Unlike conventional frequency locked loops, the frequency detector receives the inputs from binary rate multipliers, which operate independently of whether the input factors require complex reduction; this is, independently of whether M and. N are large and relatively prime the circuit is not burdened with slow correction, since the binary rate multipliers are not dependent on the reducibility of the respective input factors. The invention provides a circuit configuration that operates faster and better that any conventional design and that has no inherent pole in the loop. Furthermore, a circuit configured according to the invention operates independent of whether M and N are relatively large irreducible numbers, such as prime numbers.
Abstract translation: 本发明提供一种频率锁定环路和相关方法，其能够以改进的稳定性转换信号频率。 体现本发明的锁频环包括用于接收输入信号的输入端和用于输出具有与输入频率不同的频率的输出信号的输出。 频率检测器被配置为从主信道和第二因子输入从次信道接收第一因子输入，以计算第一因子输入和第二因子输入之间的差，并且基于第二因子输入 两个因素投入。 压控振荡器被配置为接收来自频率检测器的输出并产生输出信号。 压控振荡器最终根据频率检测器的输出设定输出频率。 与常规频率锁定环不同，频率检测器接收来自二进制速率乘法器的输入，其独立于输入因子是否需要复杂的降低; 这是独立于M和。 由于二进制比例乘法器不依赖于相应的输入因子的可还原性，所以电路不加负载，并且相对较大。 本发明提供了一种电路配置，其更快更好地操作任何常规设计，并且在环路中没有固有的极点。 此外，根据本发明配置的电路独立于M和N是否相对较大的不可约数，例如素数。
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公开(公告)号：US20210330279A1
公开(公告)日：2021-10-28
申请号：US17241417
申请日：2021-04-27
Applicant: ESS Technology, Inc.
Inventor： Dustin Dale Forman , Christian Leth Petersen , A. Martin Mallinson
Abstract: An improved method and apparatus for detecting and measuring one or more biometric parameters of a user using a computing device in conjunction with an electroacoustic (audio) transducer is described. A first mode in which the audio transducer produces sound is disabled, and the device is placed in a second mode of operation in which a biometric signal is recovered from the transducer using a “back” audio signal. The biometric signal may then be measured or analyzed. The first mode is disabled by temporarily creating a high impedance between circuitry producing the audio signal and the transducer, while the biometric parameter is measured. This allows for detection of the biometric event without the need for significant additional components or circuitry. The computing device may most conveniently be a smartphone, but the approach described herein may also be easily and usefully applied to tablets, laptop or desktop computers or other devices.
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公开(公告)号：US10433046B2
公开(公告)日：2019-10-01
申请号：US16130979
申请日：2018-09-13
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson , Robert Lynn Blair , Christian Leth Petersen , Paul Christopher Scowen
Abstract: An improved system and method for reducing the ambient noise experienced by a user listening to an earpiece without the use of a microphone is disclosed. An “ambient noise signal” created by the sound pressure wave of the ambient noise acting on the earpiece transducer is obtained. In some embodiments, the ambient noise signal is inverted and fed back, and the inverted signal is added to the intended audio signal being sent to the earpiece so that the ambient noise is cancelled. In other embodiments, a processor receives the ambient noise signal and predicts the modification to the intended audio signal needed to counteract the ambient noise. The ambient noise signal may be obtained by comparing the actual signal across the earpiece transducer to the intended audio signal, or by detecting variations in the current across the transducer from the current generated to drive the transducer.
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公开(公告)号：US20180184983A1
公开(公告)日：2018-07-05
申请号：US15574105
申请日：2016-05-13
Applicant: Lionsgate Technologies, Inc. , ESS Technology, Inc.
Inventor： Christian Leth PETERSEN , A. Martin MALLINSON
CPC classification number: A61B5/7278 , A61B5/022 , A61B5/02416 , A61B5/0816 , A61B5/7203 , A61B5/7221 , A61B5/7257
Abstract: A method for determining a physiological parameter comprises receiving measured physiological data, parsing the measured physiological data into a plurality of time windows, each time window including a plurality of samples of the physiological data, fitting each of the plurality of time windows to a mathematical function utilizing a fitting function to obtain a plurality of sets of fit parameters, each set associated with a one of the plurality of time windows, and based on the plurality of sets of fit parameters, determining a physiological parameter.
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50.发明申请公开(公告)号：US20170280244A1
公开(公告)日：2017-09-28
申请号：US15461071
申请日：2017-03-16
Applicant: ESS Technology, Inc.
Inventor： Shawn William Scarlett , Peter John Frith
CPC classification number: H04R5/04 , H04R5/033 , H04R29/001 , H04R2420/01 , H04R2420/05 , H04R2499/11
Abstract: An approach is disclosed for achieving improved sound quality from mobile ‘hifi’ playback devices by driving compatible headphones in ‘balanced’ or ‘differential’ mode via standard size headphone connectors, while retaining full compliance with legacy jack connections and allowing use of a microphone. When a headphone is connected, a smartphone may determine whether the headphone is one capable of accepting balanced audio signals, or one that uses a conventional 4-pole CTIA or OMTP jack. For a headphone that accepts balanced audio signals, the four poles of a 4-pole jack are used to drive left and right audio channels, and inverted left and right audio channels. For conventional 4-pole jacks, switches in the smartphone adapt the audio output signals to the configuration expected by the headphone and allow the smartphone to receive input from the microphone. A switch may be used to alternate between the balanced and conventional CTIA or OMTP mode.
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