公开(公告)号：US20240402426A1

公开(公告)日：2024-12-05

申请号：US18203321

申请日：2023-05-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Ryan Sporer ,  Karen Nummy

IPC: G02B6/124 ,  G02B6/13

Abstract: Structures for a photonics chip that include a reflector and methods of forming such structures. The structure comprises a reflector including a dielectric layer on a semiconductor substrate, a plurality of trenches in the dielectric layer, and a reflector layer. Each trench includes a plurality of sidewalls, and the reflector layer includes a portion on the sidewalls of each trench. The structure further comprises a photonic component over the reflector.

公开(公告)号：US12159926B2

公开(公告)日：2024-12-03

申请号：US18373598

申请日：2023-09-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Alexander Derrickson ,  Jagar Singh ,  Vibhor Jain ,  Andreas Knorr ,  Alexander Martin ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

公开(公告)号：US20240395869A1

公开(公告)日：2024-11-28

申请号：US18790086

申请日：2024-07-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xinshu CAI ,  Shyue Seng TAN ,  Vibhor JAIN ,  John J. PEKARIK ,  Robert J. GAUTHIER, JR.

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L29/739

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.

公开(公告)号：US20240389467A1

公开(公告)日：2024-11-21

申请号：US18197147

申请日：2023-05-15

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Eng-Huat Toh ,  Soh Yun Siah ,  Young Seon You ,  Kazutaka Yamane ,  Vinayak Bharat Naik ,  Chan Tze Ho Simon

IPC: H10N50/80 ,  H10N50/01

Abstract: Structures including a magnetic-tunnel-junction device and methods of forming such structures. The structure comprises a magnetic-tunnel-junction device that includes a first electrode having a first sidewall, a second electrode having a second sidewall facing the first sidewall of the first electrode, a pinned layer adjacent to the first sidewall of the first electrode, a free layer adjacent to the second sidewall of the second electrode, and a tunnel barrier layer between the free layer and the pinned layer.

公开(公告)号：US20240381794A1

公开(公告)日：2024-11-14

申请号：US18195414

申请日：2023-05-10

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan

IPC: H01L29/94

Abstract: Structures for a non-volatile programmable device and methods of forming a structure for a non-volatile programmable device. The structure comprises a first electrode including a corner and a sidewall that extends to the corner, a first dielectric layer adjacent to the first sidewall, a second dielectric layer adjacent to the first dielectric layer, and a second electrode including a portion inside a recess between the first dielectric layer and the second dielectric layer. The portion of the second electrode is disposed adjacent to the corner of the first electrode.

公开(公告)号：US12136649B2

公开(公告)日：2024-11-05

申请号：US17723665

申请日：2022-04-19

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Jianbo Zhou ,  Shiang Yang Ong ,  Namchil Mun ,  Hung Chang Liao ,  Zhongxiu Yang

IPC: H01L29/00 ,  H01L21/762 ,  H01L29/06

Abstract: Semiconductor structures including a deep trench isolation structure and methods of forming a semiconductor structure including a deep trench isolation structure. The semiconductor structure includes a semiconductor substrate having a device region, and a deep trench isolation structure in the semiconductor substrate. The deep trench isolation structure further includes a first portion, a second portion adjacent to the first portion, and a conductor layer in the first portion and the second portion. The conductor layer in the first portion of the deep trench isolation structure surrounds the device region. The conductor layer in the second portion of the deep trench isolation structure defines an electrical connection to the semiconductor substrate.

公开(公告)号：US20240365566A1

公开(公告)日：2024-10-31

申请号：US18140677

申请日：2023-04-28

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Kai Kang ,  Curtis Chun-I Hsieh ,  Jianxun Sun ,  Juan Boon Tan

IPC: H10B63/00

CPC classification number: H10B63/80

Abstract: Structures for a resistive random-access memory element and methods of forming a structure for a resistive random-access memory element. The structure comprises an interlayer dielectric layer including a first trench having a sidewall and a second trench having a sidewall adjacent to the sidewall of the first trench. The structure further comprises a first layer on the sidewall of the first trench, a second layer inside the second trench, and a third layer on the sidewall of the second trench. The first layer comprises a first metal, the second layer comprises a second metal, and the third layer comprises a dielectric material. The third layer includes a portion positioned between the first layer and the second layer.

公开(公告)号：US20240363741A1

公开(公告)日：2024-10-31

申请号：US18767418

申请日：2024-07-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar SINGH

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.

公开(公告)号：US20240361529A1

公开(公告)日：2024-10-31

申请号：US18139128

申请日：2023-04-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Keith Donegan ,  Thomas Houghton ,  Yusheng Bian ,  Karen Nummy ,  Kevin Dezfulian ,  Takako Hirokawa

IPC: G02B6/30 ,  G02B6/42

CPC classification number: G02B6/305 ,  G02B6/42 ,  G02B6/4206

Abstract: Structures including a cavity adjacent to an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate including a cavity with a sidewall, a dielectric layer on the semiconductor substrate, and an edge coupler on the dielectric layer. The structure further comprises a fill region including a plurality of fill features adjacent to the edge coupler. The fill region includes a reference marker at least partially surrounded by the plurality of fill features, and the reference marker has a perimeter that surrounds a surface area of the dielectric layer, and the surface area overlaps with a portion of the sidewall of the cavity.

公开(公告)号：US12131904B2

公开(公告)日：2024-10-29

申请号：US17934220

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

CPC classification number: H01L21/02433 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.