公开(公告)号：US07800143B2

公开(公告)日：2010-09-21

申请号：US11615982

申请日：2006-12-24

Applicant: Hyun-Jin Cho

Inventor： Hyun-Jin Cho

IPC: H01L29/76 ,  H01L29/94 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082

CPC classification number: H01L27/1021 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/1203

Abstract: A memory cell and methods of making and operating the same are provided. In one aspect, a method of forming a memory cell is provided that includes forming a MOS transistor that has a gate, a source region and a drain region. A bipolar transistor is formed that has a collector, a base and an emitter. The emitter of the bipolar transistor is formed to serve as the source region for the MOS transistor and the base of the bipolar transistor is formed to serve as a capacitive charge storage region for the memory cell.

Abstract translation: 提供了一种存储单元及其制作和操作方法。 一方面，提供一种形成存储单元的方法，包括形成具有栅极，源极区和漏极区的MOS晶体管。 形成具有集电极，基极和发射极的双极晶体管。 双极晶体管的发射极被形成为用于MOS晶体管的源极区域，并且双极晶体管的基极形成为用作存储器单元的电容电荷存储区域。

公开(公告)号：US20100144106A1

公开(公告)日：2010-06-10

申请号：US12330282

申请日：2008-12-08

Applicant: Hyun-Jin CHO ,  Sang H. DHONG ,  Jung-Suk GOO ,  Gurupada MANDAL

Inventor： Hyun-Jin CHO ,  Sang H. DHONG ,  Jung-Suk GOO ,  Gurupada MANDAL

IPC: H01L21/8242

CPC classification number: H01L27/10802 ,  H01L27/108 ,  H01L27/1082 ,  H01L27/1087 ,  H01L29/7841

Abstract: A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.

Abstract translation: 提供一种制造存储单元的方法。 在包括半导体层的半导体结构中形成沟槽，并且在沟槽中形成沟槽电容器。 将导电性确定杂质注入到半导体结构中以在直接耦合到沟槽电容器的半导体层中形成阱区。 形成覆盖阱区域的一部分的栅极结构。 然后将确定电导的离子注入阱区的其它部分以形成源区和漏区，并且在源区和漏区之间限定有源体区。 有源体区域直接接触沟槽电容器。

公开(公告)号：US20100142263A1

公开(公告)日：2010-06-10

申请号：US12707519

申请日：2010-02-17

Applicant: Hyun-Jin Cho

Inventor： Hyun-Jin Cho

IPC: G11C11/00 ,  H01L21/8249 ,  H03K3/01

CPC classification number: G11C13/0004

Abstract: A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar transistor is provided that has a collector, a base and an emitter. The body region of the MOS transistor serves as the base of the bipolar transistor and the drain region of the MOS transistor serves as the collector of the bipolar transistor. Activation of the MOS transistor causes the bipolar transistor to turn on. The MOS transistor is activated to turn on the bipolar transistor and the bipolar transistor delivers current to the source region.

Abstract translation: 提供了一种开关装置及其制作和操作方法。 一方面，提供一种操作开关器件的方法，其包括提供具有栅极，源极区域，漏极区域和体区域的MOS晶体管。 提供了具有集电极，基极和发射极的双极晶体管。 MOS晶体管的体区用作双极晶体管的基极，MOS晶体管的漏极区域用作双极晶体管的集电极。 MOS晶体管的激活导致双极晶体管导通。 MOS晶体管被激活以导通双极晶体管，并且双极晶体管将电流传送到源极区域。

公开(公告)号：US20090298238A1

公开(公告)日：2009-12-03

申请号：US12128908

申请日：2008-05-29

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: H01L21/332

CPC classification number: H01L27/1027 ,  G11C11/39 ,  H01L27/0817

Abstract: A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure. A first source region is formed adjacent the first gate structure, a common drain/cathode region is formed between the first and second gate structures, a second source region is formed adjacent the third gate structure, a common drain/source region is formed between the third and fourth gate structures, and a drain region is formed adjacent the fourth gate structure. A first base region is formed that extends into the first well region under the insulating spacer block adjacent the first gate structure, and an anode region is formed in the first well region that extends into the first well region adjacent the first base region.

Abstract translation: 提供了一种用于制造存储器件的方法。 提供半导体层，其包括在半导体层中的第一导电类型的第一，第二，第三和第四阱区。 第一栅极结构覆盖第一阱区，第二栅极结构覆盖第二阱区，第三栅极结构覆盖第三阱区，并与第二栅极结构成一体，第四栅极结构覆盖第四阱区。 在第一栅极结构的第一侧壁和第二至第四栅极结构的侧壁附近形成侧壁间隔物。 此外，绝缘间隔块形成在第一阱区的一部分和第一栅结构的一部分之上。 绝缘间隔块与第一栅极结构的第二侧壁相邻。 第一源极区域与第一栅极结构相邻地形成，在第一和第二栅极结构之间形成共同的漏极/阴极区域，在第三栅极结构附近形成第二源极区域，在第二栅极/ 第三和第四栅极结构，并且与第四栅极结构相邻形成漏极区。 形成第一基极区域，其延伸到与第一栅极结构相邻的绝缘间隔块下方的第一阱区域中，并且阳极区域形成在第一阱区域中，该第一阱区域延伸到与第一基极区域相邻的第一阱区域。

公开(公告)号：US20090296463A1

公开(公告)日：2009-12-03

申请号：US12128901

申请日：2008-05-29

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: G11C11/39

CPC classification number: H01L27/1027 ,  G11C11/39 ,  H01L27/0817

Abstract: A memory device is provided which includes a write bit line, a read bit line, and at least one memory cell. The memory cell includes a write access transistor, a read access transistor coupled to the read bit line and to the first write access transistor, and a gated-lateral thyristor (GLT) device coupled to the first write access transistor. Among its many features, the memory cell prevents read disturbances during read operations by decoupling the read and write bit lines.

Abstract translation: 提供了一种存储器件，其包括写位线，读位线和至少一个存储器单元。 存储单元包括写入存取晶体管，耦合到读取位线和第一写入存取晶体管的读取存取晶体管，以及耦合到第一写入存取晶体管的门控晶闸管（GLT）器件。 在其许多特征中，存储器单元通过去读取和写入位线来防止在读取操作期间的读取干扰。

公开(公告)号：US20090077642A1

公开(公告)日：2009-03-19

申请号：US12040355

申请日：2008-02-29

Applicant: Young-Ik EOM ,  Kwang-Sun Ko ,  Hyun-Su Jang ,  Hyun-jin Cho ,  Yong-Woo Jung ,  Hyun-Woo Choi ,  Gye-Hyeon Gyeong ,  Jung-Hwan Choi ,  Zhen Zhao ,  Tae-Hyoung Kim ,  Youn-Woo Kim

Inventor： Young-Ik EOM ,  Kwang-Sun Ko ,  Hyun-Su Jang ,  Hyun-jin Cho ,  Yong-Woo Jung ,  Hyun-Woo Choi ,  Gye-Hyeon Gyeong ,  Jung-Hwan Choi ,  Zhen Zhao ,  Tae-Hyoung Kim ,  Youn-Woo Kim

IPC: H04L9/32 ,  G06F21/00

CPC classification number: H04L63/164

Abstract: The present invention relates to a method of embodying a cooperation system between SEND and IPSec in an IPv6 environment. The cooperation system between SEND and IPSec in accordance with the present invention includes: receiving an authentication completion report message including a first IP address of a host whose authentication is completed by the SEND; generating new authentication information corresponding to the host and storing the new authentication information in a temporary storage area, if authentication information for the host is not present in the temporary storage area, wherein the authentication information includes the first IP address; and if an authentication check request message including a second IP address is received from the IPSec, checking whether the second IP address is present in the temporary storage area, and sending the result of checking to the IPSec. The present invention allows the authentication information shared between SEND and IPSec in a mobile environment, where the network is frequently accessed, enabling IPSec secure communication at a lower cost.

Abstract translation: 本发明涉及在IPv6环境中体现SEND与IPSec之间的协作系统的方法。 根据本发明的SEND和IPSec之间的协作系统包括：接收认证完成报告消息，该消息包括通过SEND完成认证的主机的第一IP地址; 生成与所述主机对应的新认证信息，并将所述新认证信息存储在临时存储区域中，如果所述主机的认证信息不存在于所述临时存储区域中，则所述认证信息包括所述第一IP地址; 并且如果从IPSec接收到包含第二IP地址的认证检查请求消息，则检查该临时存储区域中是否存在第二IP地址，并向IPSec发送检查结果。 本发明允许在经常访问网络的移动环境中在SEND和IPSec之间共享的认证信息以更低的成本实现IPSec安全通信。

公开(公告)号：US07488626B1

公开(公告)日：2009-02-10

申请号：US11483859

申请日：2006-07-10

Applicant: Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

Inventor： Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

IPC: H01L29/72

CPC classification number: G11C11/39 ,  H01L29/7436 ,  H01L29/749

Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Abstract translation: 在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。 可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。 因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。 在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

公开(公告)号：US20080242009A1

公开(公告)日：2008-10-02

申请号：US11692313

申请日：2007-03-28

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: H01L21/332

CPC classification number: H01L27/1027

Abstract: A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure. A drain region and a source/base region are formed in the semiconductor substrate adjacent the first gate structure and a cathode region is formed in the semiconductor substrate adjacent the second gate structure. The drain region, the source/base region, and the cathode region have a second conductivity type. An anode region of the first conductivity type is formed adjacent the second gate structure in a portion of the source/base region.

Abstract translation: 提供了一种用于制造存储器件的方法。 提供一种半导体衬底，其包括具有第一导电类型的第一阱区，具有第一导电类型的第二阱区，覆盖第一阱区的第一栅极结构和覆盖第二阱区的第二栅极结构。 绝缘材料层被共面沉积在半导体衬底的暴露部分上。 在绝缘材料层的覆盖在第二阱区的一部分上的部分上提供感光材料。 感光材料暴露绝缘材料层的部分。 绝缘材料层的暴露部分被各向异性蚀刻以提供与第二栅极结构的第一侧壁相邻的侧壁间隔件，以及形成在第二栅极结构的一部分上并且邻近第二栅极结构的第二侧壁的绝缘间隔块 。 漏极区域和源极/基极区域形成在与第一栅极结构相邻的半导体衬底中，并且阴极区域形成在邻近第二栅极结构的半导体衬底中。 漏极区域，源极/基极区域和阴极区域具有第二导电类型。 第一导电类型的阳极区域在源极/基极区域的一部分中与第二栅极结构相邻形成。

公开(公告)号：US20060139996A1

公开(公告)日：2006-06-29

申请号：US11361334

申请日：2006-02-24

Applicant: Farid Nemati ,  Hyun-jin Cho ,  Robert Igehy

Inventor： Farid Nemati ,  Hyun-jin Cho ,  Robert Igehy

IPC: G11C11/34

CPC classification number: G11C11/39

Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

公开(公告)号：US07042759B2

公开(公告)日：2006-05-09

申请号：US11112090

申请日：2005-04-22

Applicant: Farid Nemati ,  Hyun-Jin Cho ,  Robert Homan Igehy

Inventor： Farid Nemati ,  Hyun-Jin Cho ,  Robert Homan Igehy

IPC: G11C11/00

CPC classification number: G11C11/39

Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Abstract translation: 使用动态操作的恢复电路将电压或电流恢复脉冲信号施加到基于晶闸管的存储器单元，并且其中使用晶闸管的内部正反馈回路在单元中恢复数据。 在一个示例实现中，晶闸管中的内部正反馈环路用于在晶闸管电流下降到保持电流以下之前恢复器件的导通状态。 定义并施加脉冲和/或周期波形以确保晶闸管不从其导通状态释放。 晶闸管周期性恢复电流的时间平均值可能低于保持电流阈值。 虽然不一定限于基于晶闸管的存储器单元，但是已经发现本发明的各种实施例对于其中使用薄电容耦合晶闸管来提供双向的高速，低功率存储器单元特别有用 稳定存储元件