公开(公告)号：US20050041506A1

公开(公告)日：2005-02-24

申请号：US10959804

申请日：2004-10-06

Applicant: Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

Inventor： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/408 ,  G11C7/00

CPC classification number: G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

Abstract: Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

Abstract translation: 执行PASR（部分阵列自刷新）操作的系统和方法，其中对一个或多个部分（例如，1 / 2,1 / 8或{分数（1/16））的一部分执行用于对存储数据进行再充电的刷新操作 在一个方面，通过（1）在自刷新操作期间通过行地址计数器控制行地址的生成来执行PASR操作，以及（2）控制自身的自身 - 刷新周期产生电路，用于调整其自刷新周期输出，在PASR操作期间以减少电流消耗的方式调整自刷新周期，另一方面，通过控制一个PASR操作来执行PASR操作 或更多行对应于自刷新操作期间的部分单元阵列的行地址，从而通过阻止存储器组的未使用块的激活来实现自刷新电流消耗的减少。

公开(公告)号：US06590822B2

公开(公告)日：2003-07-08

申请号：US09925812

申请日：2001-08-09

Applicant: Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

Inventor： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

IPC: G11C700

CPC classification number: G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

Abstract: Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

Abstract translation: 执行PASR（部分阵列自刷新）操作的系统和方法，其中对一个或多个所选择的存储体的一部分（例如，1/2，1/8或1/16）执行用于对存储的数据进行再充电的刷新操作 包括半导体存储器件中的单元阵列。 一方面，通过以下操作来执行PASR操作：（1）在自刷新操作期间通过行地址计数器控制行地址的生成，以及（2）控制自刷新周期发生电路以调整自刷新周期输出 由此。 调整自刷新周期，从而在PASR操作期间降低电流消耗。 在另一方面，通过在自刷新操作期间控制对应于部分单元阵列的一个或多个行地址来执行PASR操作，由此通过阻止未使用的激活来实现自刷新电流消耗的减少 一块记忆库。

公开(公告)号：US6058063A

公开(公告)日：2000-05-02

申请号：US187544

申请日：1998-11-06

Applicant: Hyun-soon Jang

Inventor： Hyun-soon Jang

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/413 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/0175 ,  G11C7/00

CPC classification number: G11C7/1084 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/1078

Abstract: Integrated circuit memory devices (e.g., SDRAM) include an input buffer and a power reduction control circuit which disables the input buffer in response to an inactive chip select signal (CSB). The input buffer comprises a first differential amplifier having a first input electrically coupled to an input signal line (PX) and a first pull-up transistor electrically connected in series between a pull-up reference node of the first differential amplifier and a power supply signal line (e.g., Vcc). The output of the power reduction control circuit is electrically connected to a gate electrode of the first pull-up transistor. The first pull-up transistor can be turned off in response to an inactive chip select signal (CSB=1), to thereby electrically disconnect the first differential amplifier from its power supply. The input buffer may also comprise a first pull-down transistor electrically connected in series between an output of the first differential amplifier and a reference potential signal line (e.g., GND) and the output of the power reduction control circuit is electrically connected to a gate electrode of the first pull-down transistor.

Abstract translation: 集成电路存储器件（例如，SDRAM）包括输入缓冲器和功率降低控制电路，其响应于非活动芯片选择信号（CSB）禁用输入缓冲器。 输入缓冲器包括具有电耦合到输入信号线（PX）的第一输入的第一差分放大器和串联地电连接在第一差分放大器的上拉参考节点和电源信号之间的第一上拉晶体管 线（例如，Vcc）。 功率降低控制电路的输出电连接到第一上拉晶体管的栅电极。 可以响应于非活动芯片选择信号（CSB = 1）而关断第一上拉晶体管，从而将第一差分放大器与其电源电断开。 输入缓冲器还可以包括串联电连接在第一差分放大器的输出端和参考电位信号线（例如，GND）之间的第一下拉晶体管，并且功率降低控制电路的输出电连接到栅极 第一下拉晶体管的电极。

公开(公告)号：US5838990A

公开(公告)日：1998-11-17

申请号：US905562

申请日：1997-08-04

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F9/00 ,  G06F13/16

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5835956A

公开(公告)日：1998-11-10

申请号：US822148

申请日：1997-03-17

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F13/16

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5703828A

公开(公告)日：1997-12-30

申请号：US580622

申请日：1995-12-29

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5196913A

公开(公告)日：1993-03-23

申请号：US634797

申请日：1990-12-28

Applicant: Chang-Hyun Kim ,  Hyun-Soon Jang

Inventor： Chang-Hyun Kim ,  Hyun-Soon Jang

IPC: H01L27/02 ,  H02H7/20

CPC classification number: H01L27/0248 ,  H02H7/20

Abstract: This invention provides an input protection device having, within a body of semiconductor material, parallel, doped regions providing an input circuit and a charge collection area for protecting against static electricity charges at the input stage of semiconductor devices, the device including a low resistance layer formed on the body overlying the input circuit which is connected to an input pad on the body. Shortening the input signal delay time is thus attained.

Abstract translation: 本发明提供一种输入保护装置，其在半导体材料体内具有平行的掺杂区域，提供输入电路和用于在半导体器件的输入级防止静电电荷的电荷收集区域，该器件包括低电阻层 形成在身体上，覆盖连接到身体上的输入板的输入电路。 从而达到缩短输入信号延迟时间。