公开(公告)号：USD696343S1

公开(公告)日：2013-12-24

申请号：US29415218

申请日：2012-03-08

Applicant: Jong-Kyu Kim ,  Min-Chul Kim ,  Seung-Wook Jeong

Designer： Jong-Kyu Kim ,  Min-Chul Kim ,  Seung-Wook Jeong

公开(公告)号：USD695339S1

公开(公告)日：2013-12-10

申请号：US29427369

申请日：2012-07-17

Applicant: Naoto Fukasawa ,  Jong-Kyu Kim ,  Seung-Wook Jeong

Designer： Naoto Fukasawa ,  Jong-Kyu Kim ,  Seung-Wook Jeong

公开(公告)号：US08502266B2

公开(公告)日：2013-08-06

申请号：US12923195

申请日：2010-09-08

Applicant: Min-Ho Kim ,  Martin F. Schubert ,  Jong Kyu Kim ,  E. Fred Schubert ,  Yongjo Park ,  Cheolsoo Sone ,  Sukho Yoon

Inventor： Min-Ho Kim ,  Martin F. Schubert ,  Jong Kyu Kim ,  E. Fred Schubert ,  Yongjo Park ,  Cheolsoo Sone ,  Sukho Yoon

IPC: H01L33/00

CPC classification number: H01L33/02 ,  H01L33/04 ,  H01L33/32

Abstract: A nitride semiconductor light emitting device includes n-type and p-type nitride semiconductor layers, and an active layer disposed between the n-type and p-type nitride semiconductor layers and having a stack structure in which a plurality of quantum barrier layers and one or more quantum well layers are alternately stacked. A net polarization of the quantum barrier layer is smaller than or equal to a net polarization of the quantum well layer. A nitride semiconductor light emitting device can be provided, which can realize high efficiency even at high currents by minimizing the net polarization mismatch between the quantum barrier layer and the quantum well layer. Also, a high-efficiency nitride semiconductor light emitting device can be achieved by reducing the degree of energy-level bending of the quantum well layer.

Abstract translation: 氮化物半导体发光器件包括n型和p型氮化物半导体层，以及设置在n型和p型氮化物半导体层之间的有源层，并且具有堆叠结构，其中多个量子势垒层和一个 或更多量子阱层交替堆叠。 量子势垒层的净极化小于或等于量子阱层的净极化。 可以提供氮化物半导体发光器件，其可以通过最小化量子势垒层和量子阱层之间的净极化失配而在高电流下实现高效率。 此外，可以通过降低量子阱层的能量级弯曲的程度来实现高效率的氮化物半导体发光器件。

公开(公告)号：USD682928S1

公开(公告)日：2013-05-21

申请号：US29418386

申请日：2012-04-16

Applicant: Min-Chul Kim ,  Jong-Kyu Kim ,  Seung-Wook Jeong

Designer： Min-Chul Kim ,  Jong-Kyu Kim ,  Seung-Wook Jeong

公开(公告)号：US08315145B2

公开(公告)日：2012-11-20

申请号：US13107147

申请日：2011-05-13

Applicant: Jin-gyo Seo ,  Seong-sin Joo ,  Du-seop Yoon ,  Myung-do Roh ,  Yong-jin Ahn ,  Seoung-soo Kim ,  Kyung-geun Lee ,  Myeong-ho Cho ,  Chang-Jin Yang ,  Jong-kyu Kim ,  Sung-ro Ko ,  Tatsuhiro Ohtsuka

Inventor： Jin-gyo Seo ,  Seong-sin Joo ,  Du-seop Yoon ,  Myung-do Roh ,  Yong-jin Ahn ,  Seoung-soo Kim ,  Kyung-geun Lee ,  Myeong-ho Cho ,  Chang-Jin Yang ,  Jong-kyu Kim ,  Sung-ro Ko ,  Tatsuhiro Ohtsuka

IPC: G11B7/00 ,  G11B7/24

CPC classification number: G11B7/00456 ,  G11B7/0062 ,  G11B7/00718 ,  G11B7/126 ,  G11B7/1267 ,  G11B20/10009

Abstract: An optical recording medium is provided, the optical recording medium including a plurality of zones configured to store data corresponding to an adaptive write pulse, the adaptive write pulse including a first pulse, a last pulse, and a multi-pulse train, the adaptive write pulse being different for each of the plurality of zones, the plurality of zones being reflected by a grouping table, the grouping table being configured to generate an adaptive write pulse waveform by varying a position of a rising edge of a first pulse of a mark to be written according to a length of the mark to be written and a leading space, the adaptive write pulse waveform being generated without regard for a trailing space of a present mark being written using the adaptive write pulse waveform, the adaptive write pulse being configured to correspond to the adaptive write pulse waveform, and store rising edge data of the first pulse of the adaptive write pulse waveform varying according to corresponding stored values of lengths of marks to be written. A width of the first pulse is varied by varying the position of the rising edge.

Abstract translation: 提供了一种光记录介质，所述光记录介质包括配置为存储对应于自适应写入脉冲的数据的多个区域，所述自适应写入脉冲包括第一脉冲，最后脉冲和多脉冲串，所述自适应写入 所述多个区域由分组表反射，所述分组表经配置以通过将标记的第一脉冲的上升沿的位置改变为 根据要写入的标记的长度和前导空间来写入，自适应写脉冲波形在不考虑使用自适应写入脉冲波形写入的当前标记的尾部空间的情况下产生，自适应写入脉冲被配置为 对应于自适应写入脉冲波形，并且存储自适应写入脉冲波形的第一脉冲的上升沿数据根据相应的存储而变化 要写入的标记长度的d值。 通过改变上升沿的位置来改变第一脉冲的宽度。

公开(公告)号：US08305857B2

公开(公告)日：2012-11-06

申请号：US13107333

申请日：2011-05-13

Applicant: Jin-gyo Seo ,  Seong-sin Joo ,  Du-seop Yoon ,  Myung-do Roh ,  Yong-jin Ahn ,  Seoung-soo Kim ,  Kyung-geun Lee ,  Myeong-ho Cho ,  Chang-Jin Yang ,  Jong-kyu Kim ,  Sung-ro Ko ,  Tatsuhiro Ohtsuka

Inventor： Jin-gyo Seo ,  Seong-sin Joo ,  Du-seop Yoon ,  Myung-do Roh ,  Yong-jin Ahn ,  Seoung-soo Kim ,  Kyung-geun Lee ,  Myeong-ho Cho ,  Chang-Jin Yang ,  Jong-kyu Kim ,  Sung-ro Ko ,  Tatsuhiro Ohtsuka

IPC: G11B7/00

CPC classification number: G11B7/00456 ,  G11B7/0062 ,  G11B7/00718 ,  G11B7/126 ,  G11B7/1267 ,  G11B20/10009

Abstract: An apparatus configured to write input data on an optical recording medium using a write pulse waveform, the write pulse waveform including a first pulse, a last pulse and a multi-pulse train, is provided. The apparatus includes a discriminator configured to discriminate a magnitude of a present mark and a magnitude of a leading space from the input data, a write waveform controller configured to control the write pulse waveform to generate an adaptive write pulse waveform by varying a position of a rising edge of a first pulse of the present mark to be written according to the magnitude of the present mark and the magnitude of the leading space, and use a grouping table to control the write pulse waveform to generate the adaptive write pulse waveform, the grouping table being configured to store rising edge data of the first pulse of the write pulse waveform varying according to corresponding stored values of magnitudes of present marks and magnitudes of leading spaces, and a processor configured to process the input data on the optical recording medium using the adaptive write pulse waveform. The discriminator is further configured to apply the magnitude of the present mark and the magnitude of the leading space to the write waveform controller. The adaptive write pulse waveform is generated without regard for a trailing space of the present mark being written using the adaptive write pulse waveform. A width of the first pulse is varied by varying the position of the rising edge.

Abstract translation: 一种被配置为使用写入脉冲波形将输入数据写入光学记录介质的装置，提供包括第一脉冲，最后脉冲和多脉冲串的写入脉冲波形。 该装置包括：鉴别器，被配置为鉴别当前标记的大小和前导空间的幅度与输入数据;写入波形控制器，被配置为通过改变位置来控制写入脉冲波形以产生自适应写入脉冲波形 根据当前标记的大小和前导空间的大小对当前标记的第一脉冲的上升沿进行写入，并使用分组表来控制写入脉冲波形以生成自适应写入脉冲波形，分组 表被配置为存储写入脉冲波形的第一脉冲的上升沿数据，该上升沿数据根据当前标记的大小和引导空间的幅度的相应存储值而变化，以及处理器，被配置为使用该记录介质处理光学记录介质上的输入数据 自适应写入脉冲波形。 鉴别器还被配置为将当前标记的大小和前导空间的大小应用于写入波形控制器。 产生自适应写入脉冲波形，而不考虑使用自适应写入脉冲波形写入当前标记的拖尾空间。 通过改变上升沿的位置来改变第一脉冲的宽度。

公开(公告)号：US20120225530A1

公开(公告)日：2012-09-06

申请号：US13400993

申请日：2012-02-21

Applicant: Jong-Kyu KIM ,  Sangsup Jeong ,  Kukhan Yoon ,  Junsoo Lee ,  SungII Cho ,  Yong-Joon Choi

Inventor： Jong-Kyu KIM ,  Sangsup Jeong ,  Kukhan Yoon ,  Junsoo Lee ,  SungII Cho ,  Yong-Joon Choi

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L28/91 ,  H01L21/31144 ,  H01L27/0203 ,  H01L27/10817 ,  H01L27/10852

Abstract: A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.

Abstract translation: 一种制造半导体存储器件的方法包括：使用镶嵌方法在堆叠在衬底上的下模层上形成硬掩模图案，并使用硬掩模图案蚀刻下模层作为蚀刻掩模，以在硬掩模之下限定突起 模式。 在蚀刻的下模层的顶表面上形成支撑图案，蚀刻的下模层的顶表面位于比突起的顶表面更低的水平。 形成由支撑图案支撑的下电极。

公开(公告)号：US20120132887A1

公开(公告)日：2012-05-31

申请号：US13064186

申请日：2011-03-09

Applicant: Min-Ho Kim ,  Martin F. Schubert ,  Jong Kyu Kim ,  F. Fred Schubert ,  Yongio Park ,  Cheolsoo Sone ,  Sukho Yoon

Inventor： Min-Ho Kim ,  Martin F. Schubert ,  Jong Kyu Kim ,  F. Fred Schubert ,  Yongio Park ,  Cheolsoo Sone ,  Sukho Yoon

IPC: H01L33/06

CPC classification number: H01L33/04 ,  H01L33/02 ,  H01L33/32

Abstract: A nitride semiconductor light emitting device includes n-type and p-type nitride semiconductor layers; an active layer disposed between the n-type and p-type nitride semiconductor layers and having a structure in which a plurality of quantum barrier layers and one or more quantum well layers are alternately stacked; and an electron blocking layer disposed between the active layer and the p-type nitride semiconductor layer. The electron blocking layer has a superlattice structure in which two or more layers having different compositions are alternately stacked. An absolute value of a net polarization mismatch between a material, the material having a composition corresponding to an average composition of the superlattice structure, and a quantum barrier layer adjacent to the electron blocking layer among the plurality of quantum barrier layers is less than ⅔ of an absolute value of a net polarization mismatch between AlxG1-xN(0

Abstract translation: 氮化物半导体发光器件包括n型和p型氮化物半导体层; 设置在n型和p型氮化物半导体层之间的有源层，并且具有多个量子势垒层和一个或多个量子阱层交替堆叠的结构; 以及设置在有源层和p型氮化物半导体层之间的电子阻挡层。 电子阻挡层具有超晶格结构，其中具有不同组成的两层或更多层交替堆叠。 在多个量子势垒层中，材料，具有对应于超晶格结构的平均组成的组成的材料和与电子阻挡层相邻的量子势垒层的材料之间的净偏振失配的绝对值小于 具有等于​​材料的带隙能量和不同于其的组成的Al x G 1-x N（0

公开(公告)号：US20120080695A1

公开(公告)日：2012-04-05

申请号：US13080116

申请日：2011-04-05

Applicant: Sum Geun Lee ,  Jin Cheol Shin ,  Jong Kyu Kim ,  Chang Youn Kim

Inventor： Sum Geun Lee ,  Jin Cheol Shin ,  Jong Kyu Kim ,  Chang Youn Kim

IPC: H01L33/60

CPC classification number: H01L33/60 ,  H01L27/156 ,  H01L33/08 ,  H01L33/38 ,  H01L33/46

Abstract: Exemplary embodiments of the present invention disclose a light emitting diode (LED) and a method of fabricating the same. The LED includes a substrate, a semiconductor stack arranged on the substrate, the semiconductor stack including an upper semiconductor layer having a first conductivity type, an active layer, and a lower semiconductor layer having a second conductivity type, isolation trenches separating the semiconductor stack into a plurality of regions, connectors disposed between the substrate and the semiconductor stack, the connectors electrically connecting the plurality of regions to one another, and a distributed Bragg reflector (DBR) having a multi-layered structure, the DBR disposed between the semiconductor stack and the connectors. The connectors are electrically connected to the semiconductor stack through the DBR, and portions of the DBR are disposed between the isolation trenches and the connectors.

Abstract translation: 本发明的示例性实施例公开了一种发光二极管（LED）及其制造方法。 LED包括衬底，布置在衬底上的半导体堆叠，所述半导体堆叠包括具有第一导电类型的上半导体层，有源层和具有第二导电类型的下半导体层，将半导体堆叠分离成的隔离沟槽 多个区域，设置在所述基板和所述半导体堆叠之间的连接器，所述连接器将所述多个区域彼此电连接，以及具有多层结构的分布式布拉格反射器（DBR），所述DBR布置在所述半导体堆叠和 连接器。 连接器通过DBR电连接到半导体堆叠，并且DBR的部分设置在隔离沟槽和连接器之间。

公开(公告)号：US20110195538A1

公开(公告)日：2011-08-11

申请号：US13089544

申请日：2011-04-19

Applicant: Jun Hee LEE ,  Jong Kyu KIM ,  Yeo Jin YOON

Inventor： Jun Hee LEE ,  Jong Kyu KIM ,  Yeo Jin YOON

IPC: H01L33/06

CPC classification number: H01L33/0095 ,  H01L33/20

Abstract: The present invention provides a method of fabricating a light emitting diode chip having an active layer between an N type semiconductor layer and a P type semiconductor layer. The method comprises the steps of preparing a substrate; laminating the semiconductor layers on the substrate, the semiconductor layers having the active layer between the N type semiconductor layer and the P type semiconductor layer; and forming grooves on the semiconductor layers laminated on the substrate until the substrate is exposed, whereby inclined sidewalls are formed by the grooves in the semiconductor layers divided into a plurality of chips. According to embodiments of the present invention, a sidewall of a semiconductor layer formed on a substrate of a light emitting diode chip is inclined with respect to the substrate, whereby its directional angle is widened as compared with a light emitting diode chip without such inclination. As the directional angle of the light emitting diode chip is wider, when a white light emitting device is fabricated using the light emitting diode chip and a phosphor, light uniformity can be adjusted even though the phosphor is not concentrated at the center of the device. Thus, the overall light emitting efficiency can be enhanced by reducing a light blocking phenomenon caused by the increased amount of the phosphor distributed at the center portion.

Abstract translation: 本发明提供一种制造在N型半导体层和P型半导体层之间具有有源层的发光二极管芯片的方法。 该方法包括以下步骤：制备基底; 在所述基板上层叠所述半导体层，所述半导体层具有在所述N型半导体层和所述P型半导体层之间的有源层; 以及在层叠在基板上的半导体层上形成凹槽，直到基板被暴露，由此通过划分成多个芯片的半导体层中的凹槽形成倾斜的侧壁。 根据本发明的实施例，形成在发光二极管芯片的基板上的半导体层的侧壁相对于基板倾斜，由此与没有倾斜的发光二极管芯片相比，其方向角度变宽。 随着发光二极管芯片的方位角变宽，当使用发光二极管芯片和荧光体制造白色发光器件时，即使荧光体不集中在器件的中心，也可以调整光均匀性。 因此，通过减少由分散在中心部分的荧光体的量增加引起的遮光现象，可以提高整体发光效率。