公开(公告)号：US06556507B2

公开(公告)日：2003-04-29

申请号：US10260341

申请日：2002-10-01

申请人： Haruki Toda ,  Kenji Tsuchida ,  Hitoshi Kuyama

发明人： Haruki Toda ,  Kenji Tsuchida ,  Hitoshi Kuyama

IPC分类号： G11C800

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C11/4087

摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S·N·F.

公开(公告)号：US06487133B2

公开(公告)日：2002-11-26

申请号：US09898033

申请日：2001-07-05

申请人： Masaharu Wada ,  Kenji Tsuchida ,  Atsushi Takeuchi

发明人： Masaharu Wada ,  Kenji Tsuchida ,  Atsushi Takeuchi

IPC分类号： G11C700

CPC分类号： G11C7/06

摘要： The present invention relates to overdrive circuits for generating an operational potential of a sense amplifier. For example, a switch circuit is used to connect a drive node of the sense amplifier with a overdrive potential generation circuit for generating an overdrive potential to be applied to bit lines. A restoration potential generation circuit comprises a push-pull regulator circuit for generating a restoration potential to be applied to bit lines. Consequently, the restoration potential generation circuit can directly connect with the sense amplifier's drive node.

公开(公告)号：US06484246B2

公开(公告)日：2002-11-19

申请号：US09383193

申请日：1999-08-26

申请人： Kenji Tsuchida ,  Haruki Toda ,  Hitoshi Kuyama

发明人： Kenji Tsuchida ,  Haruki Toda ,  Hitoshi Kuyama

IPC分类号： G06F1202

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281 ,  G11C2207/229

摘要： A dynamic random access memory device includes a bit line, a memory cell coupled to the bit line, and a word line coupled to the memory cell. A read activation time between receiving a read command for a read operation in order to read data: from the memory cell and activating the word-line-may be different from a write activation time between receiving a write command for a write operation in order to write data to the memory cell and activating the word line.

摘要翻译： 动态随机存取存储器件包括位线，耦合到位线的存储单元和耦合到存储器单元的字线。 为了从存储器单元读取数据和激活字线，读取操作的读取命令之间的读取激活时间可能不同于接收写入操作的写入命令之间的写入激活时间，以便于 将数据写入存储单元并激活字线。

公开(公告)号：US06326834B1

公开(公告)日：2001-12-04

申请号：US09602896

申请日：2000-06-23

申请人： Hironobu Akita ,  Masaharu Wada ,  Kenji Tsuchida ,  Hironori Banba

发明人： Hironobu Akita ,  Masaharu Wada ,  Kenji Tsuchida ,  Hironori Banba

IPC分类号： G05F110

CPC分类号： H02M3/073

摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.

摘要翻译： 用于对多个电容器的各个侧面节点进行充电的第一晶体管分别连接到电容器的这些节点。 用于输出每个电容器的电荷的第二晶体管分别连接在电容器的相应的一个侧面节点和输出端子之间。 用于将电容器的另一侧节点的电荷转移到其他节点的多个第三晶体管连接到相应的其他节点。 每个电容器的电荷通过顺序地控制第三晶体管，通过一个路径从高电位的节点被串行地传递到较低电位的节点，或者每个电容器的电荷在高电位的任意节点之间并行传送 潜在和低节点通过多个路径。 通过这些操作，每个电容器的电荷被再循环。

公开(公告)号：US06185150B2

公开(公告)日：2001-02-06

申请号：US09448412

申请日：1999-11-23

申请人： Haruki Toda ,  Kenji Tsuchida ,  Hitoshi Kuyama

发明人： Haruki Toda ,  Kenji Tsuchida ,  Hitoshi Kuyama

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078

摘要： A delay circuit produces an activation signal by delaying a clock signal by 270 degrees. A receiver circuit is responsive to the activation signal to capture a command latch enable signal indicating a command cycle and produce an internal signal corresponding to the command cycle. An AND circuit produces a command latch signal synchronized with the clock signal during an interval in which the internal signal is produced. Command receivers take command-forming signals only when the command latch signal is applied thereto. That is, these command receivers are activated only when the command latch signal is received but not at all times. This prevents power dissipation from increasing and allows a plurality of signals to be monitored reliably.

摘要翻译： 延迟电路通过将时钟信号延迟270度来产生激活信号。 接收器电路响应于激活信号以捕获指示命令周期的命令锁存使能信号并产生对应于命令周期的内部信号。 AND电路在产生内部信号的间隔期间产生与时钟信号同步的命令锁存信号。 命令接收器只有当命令锁存信号被施加到命令形成信号时才采取命令形成信号。 也就是说，这些命令接收器仅在接收到命令锁存信号时才被激活，而不是始终被激活。 这防止功率消耗增加，并且允许可靠地监视多个信号。

公开(公告)号：US6002636A

公开(公告)日：1999-12-14

申请号：US199463

申请日：1998-11-25

申请人： Kenji Tsuchida ,  Shinichiro Shiratake ,  Tsuneo Inaba

发明人： Kenji Tsuchida ,  Shinichiro Shiratake ,  Tsuneo Inaba

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C8/08 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C5/025 ,  G11C11/4085 ,  G11C8/08

摘要： This invention discloses the layout of word line driving circuits for driving word lines. A semiconductor memory device includes a memory cell array having a bit line, n memory cells connected to the bit line, and n word lines respectively connected to the n memory cells. The semiconductor memory device further includes n/2 first word line driving circuits for driving n/2 word lines of the n word lines, and n/2 second word line driving circuits for driving the remaining n/2 word lines of the n word lines. The second word line driving circuits are arranged at the positions where the second word line driving circuits face the first word line driving circuits via the memory cell array.

摘要翻译： 本发明公开了用于驱动字线的字线驱动电路的布局。 一种半导体存储器件包括具有位线的存储单元阵列，+ E，连接到位线的uns n + EE存储器单元，以及分别连接到+ E，uns n + EE的+ E，uns n + EE字线 记忆细胞 半导体存储器件还包括用于驱动+ E，n n + EE字线的n / 2个字线的n / 2个第一字线驱动电路和用于驱动剩余n / 2个字的n / 2个第二字线驱动电路 行+ E，uns n + EE字线。 第二字线驱动电路被布置在第二字线驱动电路经由存储单元阵列面对第一字线驱动电路的位置。

公开(公告)号：US5973991A

公开(公告)日：1999-10-26

申请号：US305752

申请日：1999-05-06

申请人： Kenji Tsuchida ,  Haruki Toda

发明人： Kenji Tsuchida ,  Haruki Toda

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4094 ,  G11C8/00

CPC分类号： G11C11/4094 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/002

摘要： In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted and a third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, a high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for a semiconductor chip size.

摘要翻译： 在半导体存储器系统中，SDRAM包括被分成多个单元阵列块的存储单元阵列101，列解码器，行解码器和读出放大器电路。 在SDRAM中，当进行单元阵列块中的连续访问时，设置具有第一周期时间的第一操作模式，当覆盖单元阵列的连续访问时，设置具有比第一周期时间短的第二周期时间的第二操作模式 进行彼此分开的块，并且进行覆盖彼此相邻的单元阵列块的连续访问时，设定具有中等周期时间的第三操作模式。 利用上述结构，可以在不设置特定附件电路的同时抑制半导体芯片尺寸的开销，实现高速访问。

公开(公告)号：US5703817A

公开(公告)日：1997-12-30

申请号：US748779

申请日：1996-11-14

申请人： Shinichiro Shiratake ,  Daisaburo Takashima ,  Kenji Tsuchida ,  Tsuneo Inaba

发明人： Shinichiro Shiratake ,  Daisaburo Takashima ,  Kenji Tsuchida ,  Tsuneo Inaba

IPC分类号： H01L21/82 ,  G11C11/401 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/44 ,  G11C29/804 ,  G11C29/808

摘要： A plurality of memory cells are arranged at crosspoints between a plurality of word lines and a plurality of bit lines. The memory cells include not only normal cells but also spare cells for saving defects. The saving of the defect is effected by replacing the word line or bit line connected to the normal cell with the word line or bit line connected to the spare cell. The replacement is effected by a corresponding pair of fuse circuit and deciding circuit, that is, the fuse circuit for storing the address of a word line or bit line to be replaced and the deciding circuit for, based on the address, deciding whether or not an accessed word line or bit line be replaced. As such a pair use is made of a plurality of pairs and a plurality of kinds are provided as the word lines or bit lines for replacement and can be used in accordance with the size of defects. It is, therefore, possible to effectively save the defective word line or bit line, while avoiding any uneffective replacement.

摘要翻译： 多个存储单元被布置在多个字线和多个位线之间的交叉点处。 存储单元不仅包括正常单元格，还包括用于保存缺陷的备用单元。 通过用连接到备用单元的字线或位线替换连接到正常单元的字线或位线来实现缺陷的保存。 该替换由对应的熔丝电路和判定电路对，即用于存储要替换的字线或位线的地址的熔丝电路和基于该地址的判定电路来决定是否 访问的字线或位线被替换。 这样一对使用由多对构成，并且提供多种类型作为用于替换的字线或位线，并且可以根据缺陷的尺寸使用。 因此，可以有效地保存有缺陷的字线或位线，同时避免任何不必要的更换。

公开(公告)号：US5398207A

公开(公告)日：1995-03-14

申请号：US67629

申请日：1993-05-28

申请人： Kenji Tsuchida ,  Takashi Ohsawa

发明人： Kenji Tsuchida ,  Takashi Ohsawa

IPC分类号： G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094

摘要： A MOS dynamic random access memory device has a memory cell array section formed on a semiconductor substrate, including memory cells each having a data storage capacitor and a transfer-gate transistor. Parallel bit lines are associated with the memory cell array section. Parallel word lines extend transverse to the bit lines, including a word line connected to the transfer-gate transistor. A booster circuit is arranged to provide a potentially raised voltage which is higher than a power supply voltage. A sense amplifier circuit is connected with a corresponding bit line pair of the word lines. A word-line driver circuit has an input connected to the booster circuit and an output connected to the word line. A bit-line restoring circuit is connected to the sense amplifier circuit. The restoring circuit includes a voltage-down converting metal oxide semiconductor field effect transistor having an insulated gate connected to the booster circuit, a drain coupled to the power supply voltage, and a source at which a potentially decreased voltage appears to be lower than the power supply voltage. The voltage-down converting transistor is same in channel conductivity type as the transfer-gate transistor.

摘要翻译： MOS动态随机存取存储器件具有形成在半导体衬底上的存储单元阵列部分，其包括各自具有数据存储电容器和转移栅极晶体管的存储单元。 并行位线与存储单元阵列部分相关联。 并行字线横向于位线延伸，包括连接到转移栅晶体管的字线。 升压电路被布置成提供高于电源电压的潜在升高电压。 读出放大器电路与字线对应的位线对连接。 字线驱动器电路具有连接到升压电路的输入端和连接到字线的输出。 位线恢复电路连接到读出放大器电路。 恢复电路包括具有连接到升压电路的绝缘栅极的降压转换金属氧化物半导体场效应晶体管，耦合到电源电压的漏极和潜在降低的电压似乎低于功率的源 电源电压。 降压转换晶体管的沟道导电类型与转移栅晶体管相同。

公开(公告)号：US5084842A

公开(公告)日：1992-01-28

申请号：US536718

申请日：1990-06-12

申请人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

发明人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10805 ,  G11C11/4091 ,  G11C11/4094

摘要： A dynamic random access memory has a substrate, plural pairs of parallel bit lines provided on the substrate, parallel word lines insulatively crossing the parallel bit lines to define cross points therebetween, and memory cells provided at the cross points. Each memory cell has a data storage capacitor and a transistor. Sense amplifiers are provided at bit line pairs, respectively, to sense a data voltage. A discharge control section, which is associated with the sense amplifiers, forms discharge paths branched between the bit line pairs and the substrate grounded to progress the discharging of charges, when a certain word line is designated and a memory cell is selected from those memory cells which are connected to the certain word line, whereby the operational speed of the memory is increased.

摘要翻译： 动态随机存取存储器具有衬底，设置在衬底上的多对并行位线，并行字线绝对地穿过并行位线以限定它们之间的交叉点，以及设置在交叉点处的存储单元。 每个存储单元具有数据存储电容器和晶体管。 分别在位线对处提供感测放大器以感测数据电压。 与读出放大器相关联的放电控制部分在指定某个字线并且从那些存储器单元中选择存储器单元时，形成在位线对和衬底之间分支的放电路径，从而导致电荷的放电 其连接到某个字线，由此增加存储器的操作速度。