公开(公告)号：US08460999B2

公开(公告)日：2013-06-11

申请号：US13067405

申请日：2011-05-31

Applicant: Seung-Jae Baik ,  Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Sang-Jin Hyun

Inventor： Seung-Jae Baik ,  Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Sang-Jin Hyun

IPC: H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/66833

Abstract: A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.

Abstract translation: 非易失性存储器件可以包括：半导体衬底上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层; 以及在所述阻挡绝缘层上的控制栅电极。 隧道绝缘层可以包括第一隧道绝缘层和第二隧道绝缘层。 第一隧道绝缘层和第二隧道绝缘层可以顺序堆叠在半导体衬底上。 第二隧道绝缘层可以具有比第一隧道绝缘层更大的带隙。 非易失性存储器件的制造方法可以包括：在半导体衬底上形成隧道绝缘层; 在隧道绝缘层上形成电荷存储层; 在电荷存储层上形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成控制栅电极。

公开(公告)号：US08435877B2

公开(公告)日：2013-05-07

申请号：US13227799

申请日：2011-09-08

Applicant: Jun-Kyu Yang ,  Hong-Suk Kim ,  Ju-Yul Lee ,  Ki-Hyun Hwang ,  Jae-Young Ahn

Inventor： Jun-Kyu Yang ,  Hong-Suk Kim ,  Ju-Yul Lee ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC: H01L21/28

CPC classification number: H01L21/28247 ,  H01L21/28273 ,  H01L21/764 ,  H01L27/11568

Abstract: A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein.

Abstract translation: 半导体器件包括栅极结构，其包括顺序地设置在衬底上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 控制栅极包括杂质掺杂多晶硅层图案和金属层图案。 栅极结构在衬底上彼此间隔开。 覆盖层图案设置在金属层图案的侧壁部分上并且包括金属氧化物。 绝缘层覆盖栅极结构和覆盖层图案。 绝缘层形成在基板上并且在其中包括气隙。

公开(公告)号：US20120156848A1

公开(公告)日：2012-06-21

申请号：US13239594

申请日：2011-09-22

Applicant: Sang-ryol YANG ,  Ki-hyun HWANG ,  Seung-bae PARK ,  Jin-gyun KIM ,  Woong LEE ,  Jung-geun JEE ,  Ji-hoon CHOI

Inventor： Sang-ryol YANG ,  Ki-hyun HWANG ,  Seung-bae PARK ,  Jin-gyun KIM ,  Woong LEE ,  Jung-geun JEE ,  Ji-hoon CHOI

IPC: H01L21/336 ,  H01L21/768

CPC classification number: H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A method of manufacturing a non-volatile memory device includes alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate, forming first openings exposing the substrate, forming sidewall insulating layers on sidewalls of the first openings, and forming channel regions on the sidewall insulating layers. The first openings penetrate the interlayer sacrificial layers and the interlayer insulating layers. The sidewall insulating layers have different thicknesses according to distances from the substrate.

Abstract translation: 一种制造非易失性存储器件的方法包括在衬底上交替层叠层间牺牲层和层间绝缘层，形成暴露衬底的第一开口，在第一开口的侧壁上形成侧壁绝缘层，以及在侧壁绝缘层上形成沟道区 层。 第一开口贯穿层间牺牲层和层间绝缘层。 侧壁绝缘层根据与基板的距离具有不同的厚度。

公开(公告)号：US20120149185A1

公开(公告)日：2012-06-14

申请号：US13313754

申请日：2011-12-07

Applicant: Hyo-Jung Kim ,  Ki-Hyun Hwang ,  Kyung-Hyun Kim ,  Han-Mei Choi ,  Dong-Chul Yoo ,  Chan-Jin Park ,  Jong-Heun Lim ,  Myung-Jung Pyo ,  Byoung-Moon Yoon ,  Chang-Sup Mun

Inventor： Hyo-Jung Kim ,  Ki-Hyun Hwang ,  Kyung-Hyun Kim ,  Han-Mei Choi ,  Dong-Chul Yoo ,  Chan-Jin Park ,  Jong-Heun Lim ,  Myung-Jung Pyo ,  Byoung-Moon Yoon ,  Chang-Sup Mun

IPC: H01L21/3205 ,  H01L21/311

CPC classification number: H01L21/31053 ,  H01L21/3212 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Abstract translation: 制造半导体器件的方法包括在第一区域中形成集成结构和第一停止层图案。 形成第一绝缘层和第二阻挡层。 通过部分蚀刻第一区域中的第二阻挡层和第一绝缘中间层来形成第二初步绝缘中间层。 执行第一次抛光以去除突出部分。 执行第二抛光以暴露第一和第二停止层图案。

公开(公告)号：US20120115309A1

公开(公告)日：2012-05-10

申请号：US13241316

申请日：2011-09-23

Applicant: Dong-Chul Yoo ,  Chan-Jin Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Joon-Suk Lee

Inventor： Dong-Chul Yoo ,  Chan-Jin Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Joon-Suk Lee

IPC: H01L21/28

CPC classification number: H01L27/11582 ,  H01L27/105 ,  H01L27/11573 ,  H01L27/11575

Abstract: Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.

Abstract translation: 制造半导体器件的方法包括在衬底的第一区域中形成停止层图案。 第一模具结构形成在与第一区域相邻的基板的第二区域中。 第一模具结构包括交替堆叠的第一牺牲图案和第一层间图案。 在第一模具结构和止挡层图案上形成第二模具结构。 第二模具结构包括交替堆叠的第二牺牲图案和第二层间图案。 第二模具结构部分地覆盖止挡层图案。 形成通道图案并通过第一模具结构和第二模具结构。

公开(公告)号：US20120064707A1

公开(公告)日：2012-03-15

申请号：US13227799

申请日：2011-09-08

Applicant: Jun-Kyu YANG ,  Hong-Suk Kim ,  Ju-Yul Lee ,  Ki-Hyun Hwang ,  Jae-Young Ahn

Inventor： Jun-Kyu YANG ,  Hong-Suk Kim ,  Ju-Yul Lee ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC: H01L21/28

CPC classification number: H01L21/28247 ,  H01L21/28273 ,  H01L21/764 ,  H01L27/11568

Abstract: A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein.

Abstract translation: 半导体器件包括栅极结构，其包括顺序地设置在衬底上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 控制栅极包括杂质掺杂多晶硅层图案和金属层图案。 栅极结构在衬底上彼此间隔开。 覆盖层图案设置在金属层图案的侧壁部分上并且包括金属氧化物。 绝缘层覆盖栅极结构和覆盖层图案。 绝缘层形成在基板上并且在其中包括气隙。

公开(公告)号：US20110306195A1

公开(公告)日：2011-12-15

申请号：US13099485

申请日：2011-05-03

Applicant: Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

Inventor： Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

IPC: H01L21/28

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves.

Abstract translation: 在垂直半导体器件和制造垂直半导体器件的方法中，牺牲层和绝缘夹层重叠交替堆叠在衬底上。 牺牲层包括硼（B）和氮（N），并且相对于绝缘夹层具有蚀刻选择性。 通过牺牲层和绝缘夹层在衬底上形成半导体图案。 在半导体图案之间至少部分去除牺牲层和绝缘夹层，以在半导体图案的侧壁上形成牺牲层图案和绝缘层间图案。 去除牺牲层图案以在绝缘层间图案之间形成凹槽。 凹槽暴露半导体图案的侧壁的部分。 在每个槽中形成栅极结构。

公开(公告)号：US07973355B2

公开(公告)日：2011-07-05

申请号：US12216945

申请日：2008-07-14

Applicant: Seung-Jae Baik ,  Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Sang-Jin Hyun

Inventor： Seung-Jae Baik ,  Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Sang-Jin Hyun

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/66833

Abstract: A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.

Abstract translation: 非易失性存储器件可以包括：半导体衬底上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层; 以及在所述阻挡绝缘层上的控制栅电极。 隧道绝缘层可以包括第一隧道绝缘层和第二隧道绝缘层。 第一隧道绝缘层和第二隧道绝缘层可以顺序堆叠在半导体衬底上。 第二隧道绝缘层可以具有比第一隧道绝缘层更大的带隙。 非易失性存储器件的制造方法可以包括：在半导体衬底上形成隧道绝缘层; 在隧道绝缘层上形成电荷存储层; 在电荷存储层上形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成控制栅电极。

公开(公告)号：US20110001183A1

公开(公告)日：2011-01-06

申请号：US12659357

申请日：2010-03-05

Applicant: Dong-Chul Yoo ,  Eun-Ha Lee ,  Hyung-Ik Lee ,  Ki-Hyun Hwang ,  Sung Heo ,  Han-Mei Choi ,  Yong-Koo Kyoung ,  Byong-Ju Kim

Inventor： Dong-Chul Yoo ,  Eun-Ha Lee ,  Hyung-Ik Lee ,  Ki-Hyun Hwang ,  Sung Heo ,  Han-Mei Choi ,  Yong-Koo Kyoung ,  Byong-Ju Kim

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/02145 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28282 ,  H01L21/3141 ,  H01L27/11521

Abstract: A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.

Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括在衬底上的隧道电介质层，隧道电介质层上的电荷存储层，电荷存储层上的阻挡介电层，阻挡电介质层包括具有氧化硅的第一电介质层， 所述第一电介质层具有硅酸铝，以及形成在所述第二电介质层上并具有氧化铝的第三电介质层和所述阻挡电介质层上的上电极。

公开(公告)号：US20090280615A1

公开(公告)日：2009-11-12

申请号：US12453231

申请日：2009-05-04

Applicant: Dong-Kak LEE ,  Ki-Hyun HWANG ,  Jin-Gyun KIM

Inventor： Dong-Kak LEE ,  Ki-Hyun HWANG ,  Jin-Gyun KIM

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/266

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/76829 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621

Abstract: A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.

Abstract translation: 在半导体器件中形成导电结构的方法包括在衬底上形成导电层，在衬底上形成导电层图案，通过图案化导电层，在衬底上形成氧化物层和导电层的一部分，以及 在氧化物层和导电层图案上形成覆盖层。