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    Methods of manufacturing semiconductor devices
    1.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08435877B2

    公开(公告)日：2013-05-07

    申请号：US13227799

    申请日：2011-09-08

    申请人： Jun-Kyu Yang ,  Hong-Suk Kim ,  Ju-Yul Lee ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    发明人： Jun-Kyu Yang ,  Hong-Suk Kim ,  Ju-Yul Lee ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28247 ,  H01L21/28273 ,  H01L21/764 ,  H01L27/11568

    摘要： A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein.

    摘要翻译： 半导体器件包括栅极结构，其包括顺序地设置在衬底上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 控制栅极包括杂质掺杂多晶硅层图案和金属层图案。 栅极结构在衬底上彼此间隔开。 覆盖层图案设置在金属层图案的侧壁部分上并且包括金属氧化物。 绝缘层覆盖栅极结构和覆盖层图案。 绝缘层形成在基板上并且在其中包括气隙。

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    2.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20120064707A1

    公开(公告)日：2012-03-15

    申请号：US13227799

    申请日：2011-09-08

    申请人： Jun-Kyu YANG ,  Hong-Suk Kim ,  Ju-Yul Lee ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    发明人： Jun-Kyu YANG ,  Hong-Suk Kim ,  Ju-Yul Lee ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28247 ,  H01L21/28273 ,  H01L21/764 ,  H01L27/11568

    摘要： A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein.

    摘要翻译： 半导体器件包括栅极结构，其包括顺序地设置在衬底上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 控制栅极包括杂质掺杂多晶硅层图案和金属层图案。 栅极结构在衬底上彼此间隔开。 覆盖层图案设置在金属层图案的侧壁部分上并且包括金属氧化物。 绝缘层覆盖栅极结构和覆盖层图案。 绝缘层形成在基板上并且在其中包括气隙。

    Methods of forming vertical type semiconductor devices including oxidation target layers
    4.
    发明授权
    Methods of forming vertical type semiconductor devices including oxidation target layers 有权
    形成包括氧化靶层的垂直型半导体器件的方法

    公开(公告)号：US09082659B1

    公开(公告)日：2015-07-14

    申请号：US14643527

    申请日：2015-03-10

    申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

    摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

    摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

    Vertical memory devices and methods of manufacturing the same
    5.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US09461061B2

    公开(公告)日：2016-10-04

    申请号：US14546172

    申请日：2014-11-18

    申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Hun Hyeong Lim ,  Ki-Hyun Hwang

    发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Hun Hyeong Lim ,  Ki-Hyun Hwang

    IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.

    摘要翻译： 制造垂直存储器件的方法包括在衬底上形成交替和重复的绝缘夹层和牺牲层，牺牲层包括多晶硅或非晶硅，通过绝缘夹层和牺牲层形成通道孔，在通道孔中形成通道， 蚀刻绝缘夹层的部分和相邻通道之间的牺牲层以形成开口，去除牺牲层以在绝缘夹层之间形成间隙，并在间隙中形成栅极线。

    METHODS OF FORMING VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS
    6.
    发明申请
    METHODS OF FORMING VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS 审中-公开
    形成包含氧化目标层的垂直型半导体器件的方法

    公开(公告)号：US20150187790A1

    公开(公告)日：2015-07-02

    申请号：US14643527

    申请日：2015-03-10

    申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

    摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

    摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙比第二垂直间隙宽 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

    Vertical type semiconductor devices including oxidation target layers
    7.
    发明授权
    Vertical type semiconductor devices including oxidation target layers 有权
    包括氧化靶层的垂直型半导体器件

    公开(公告)号：US08987805B2

    公开(公告)日：2015-03-24

    申请号：US13971347

    申请日：2013-08-20

    申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

    摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

    摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

    VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS
    8.
    发明申请
    VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS 有权
    垂直型半导体器件，包括氧化目标层

    公开(公告)号：US20140054676A1

    公开(公告)日：2014-02-27

    申请号：US13971347

    申请日：2013-08-20

    申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

    摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

    摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

    VERTICAL STRUCTURE NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    VERTICAL STRUCTURE NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    垂直结构非易失性存储器件及其制造方法

    公开(公告)号：US20120276696A1

    公开(公告)日：2012-11-01

    申请号：US13456415

    申请日：2012-04-26

    申请人： Jun-Kyu Yang ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn ,  Han-Mei Choi ,  Dong-Chul Yoo

    发明人： Jun-Kyu Yang ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn ,  Han-Mei Choi ,  Dong-Chul Yoo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7926 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889

    摘要： A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.

    摘要翻译： 一种垂直结构的非易失性存储器件，其中防止栅介质层向衬底突出; 降低了接地选择线（GSL）电极的电阻，使得非易失性存储器件高度集成并且具有改进的可靠性，并且提供了其制造方法。 该方法包括：在硅衬底上依次形成多晶硅层和绝缘层; 通过所述多晶硅层和所述绝缘层形成栅介质层和沟道层，所述栅介质层和所述沟道层在垂直于所述硅衬底的方向上延伸; 形成用于使所述硅衬底暴露于所述绝缘层和所述多晶硅层的开口; 通过在预定温度下使用含卤素反应气体去除通过开口暴露的多晶硅层; 并在通过去除多晶硅层形成的空间中填充金属层。