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    Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers
    41.
    发明授权
    Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers 失效
    非易失性存储器件及其编程方法，包括通过电荷陷阱层之间的衬垫氧化物层移动电子

    公开(公告)号：US07668016B2

    公开(公告)日：2010-02-23

    申请号：US12078141

    申请日：2008-03-27

    Applicant: Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park ,  Sang-moo Choi

    Inventor： Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park ,  Sang-moo Choi

    IPC: G11C16/04

    CPC classification number: G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/7923

    Abstract: Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first charge trap layer, and a second trap layer on the pad oxide layer and storing electrons. In a programming mode in which data is written, the stored electrons are moved between a first position of the first charge trap layer and a first position of the second charge trap layer through the pad oxide layer or between a second position of the first charge trap layer and a second position of the second charge trap layer through the pad oxide layer.

    Abstract translation: 提供非易失性存储器件以及通过衬垫氧化物层对电子在电荷陷阱层之间移动的非易失性存储器件进行编程的方法。 非易失性存储器件包括半导体衬底上的电荷陷阱层，并且存储电子，在第一电荷陷阱层上形成焊盘氧化物层，并且在焊盘氧化物层上存储第二陷阱层并存储电子。 在写入数据的编程模式中，所存储的电子在第一电荷陷阱层的第一位置和第二电荷陷阱层的第一位置之间通过焊盘氧化物层或第一电荷陷阱的第二位置之间移动 层和第二电荷陷阱层的第二位置穿过衬垫氧化物层。

    Method for reducing lateral movement of charges and memory device thereof
    42.
    发明申请
    Method for reducing lateral movement of charges and memory device thereof 有权
    减少电荷横向运动的方法及其记忆装置

    公开(公告)号：US20090244980A1

    公开(公告)日：2009-10-01

    申请号：US12382790

    申请日：2009-03-24

    Applicant: Kwang-soo Seol ,  Young-gu Jin ,  Yoon-dong Park

    Inventor： Kwang-soo Seol ,  Young-gu Jin ,  Yoon-dong Park

    IPC: G11C16/06

    CPC classification number: G11C16/10 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3454

    Abstract: Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the at least one erased state memory cell and verifying that the pre-programmed memory cell is in the pre-programmed state using a negative effective verifying voltage.

    Abstract translation: 提供一种用于减少电荷的横向移动的方法和装置。 该方法可以包括通过对至少一个存储器单元施加预编程电压以使得具有比所述至少一个擦除状态存储器单元更窄的阈值电压分布来对处于擦除状态的至少一个存储器单元进行预编程，以及 使用负的有效验证电压来验证预编程存储器单元是否处于预编程状态。

    Memory device having nanocrystals in memory cell
    43.
    发明授权
    Memory device having nanocrystals in memory cell 有权
    在存储器单元中具有纳米晶体的存储器件

    公开(公告)号：US07501680B2

    公开(公告)日：2009-03-10

    申请号：US11711714

    申请日：2007-02-28

    Applicant: Kwang-soo Seol ,  Seong-jae Choi ,  Jae-young Choi ,  Yo-sep Min ,  Eun-joo Jang ,  Dong-kee Yi

    Inventor： Kwang-soo Seol ,  Seong-jae Choi ,  Jae-young Choi ,  Yo-sep Min ,  Eun-joo Jang ,  Dong-kee Yi

    IPC: H01L21/336

    CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/51 ,  H01L29/513 ,  H01L29/7881 ,  Y10S977/721 ,  Y10S977/785 ,  Y10S977/943

    Abstract: The memory device includes a source region and a drain region in a substrate and spaced apart from each other; a memory cell formed on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; a control gate formed on the memory cell. The memory cell includes a first tunneling oxide layer formed on the substrate; a second tunneling oxide layer formed on the first tunneling oxide layer; and a control oxide layer formed on the second tunneling oxide layer. The control oxide layer includes the nanocrystals. The second tunneling oxide layer, having an aminosilane group the increases electrostatic attraction, may be hydrophilic, enabling the formation of a monolayer of the nanocrystals.

    Abstract translation: 该存储装置包括一基板中的一源极区和一漏极区，彼此间隔开; 形成在所述基板的表面上的存储单元，其中所述存储单元连接所述源极区域和所述漏极区域并且包括多个纳米晶体; 形成在存储单元上的控制栅极。 存储单元包括形成在基板上的第一隧穿氧化层; 形成在第一隧道氧化物层上的第二隧穿氧化物层; 以及形成在第二隧道氧化物层上的控制氧化物层。 控制氧化物层包括纳米晶体。 具有增加静电吸引力的氨基硅烷基团的第二隧道氧化物层可以是亲水性的，能够形成纳米晶体的单层。

    Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers
    44.
    发明申请
    Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers 失效
    非易失性存储器件及其编程方法，包括通过电荷陷阱层之间的衬垫氧化物层移动电子

    公开(公告)号：US20090034341A1

    公开(公告)日：2009-02-05

    申请号：US12078141

    申请日：2008-03-27

    Applicant: Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park ,  Sang-moo Choi

    Inventor： Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park ,  Sang-moo Choi

    IPC: G11C16/04 ,  H01L29/792

    CPC classification number: G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/7923

    Abstract: Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first charge trap layer, and a second trap layer on the pad oxide layer and storing electrons. In a programming mode in which data is written, the stored electrons are moved between a first position of the first charge trap layer and a first position of the second charge trap layer through the pad oxide layer or between a second position of the first charge trap layer and a second position of the second charge trap layer through the pad oxide layer.

    Abstract translation: 提供非易失性存储器件以及通过衬垫氧化物层对电子在电荷陷阱层之间移动的非易失性存储器件进行编程的方法。 非易失性存储器件包括半导体衬底上的电荷陷阱层，并且存储电子，在第一电荷陷阱层上形成焊盘氧化物层，并且在焊盘氧化物层上存储第二陷阱层并存储电子。 在写入数据的编程模式中，所存储的电子在第一电荷陷阱层的第一位置和第二电荷陷阱层的第一位置之间通过焊盘氧化物层或第一电荷陷阱的第二位置之间移动 层和第二电荷陷阱层的第二位置穿过衬垫氧化物层。

    Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same
    47.
    发明申请
    Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same 有权
    用于电荷陷阱半导体存储器件的电荷陷阱层及其制造方法

    公开(公告)号：US20080131710A1

    公开(公告)日：2008-06-05

    申请号：US11987425

    申请日：2007-11-30

    Applicant: Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

    Inventor： Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

    IPC: B32B15/04 ,  H01L21/31 ,  H01L29/792

    CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7883 ,  Y10T428/31678

    Abstract: Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.

    Abstract translation: 提供了一种在半导体衬底上包括电荷陷阱层的电荷陷阱半导体存储器件，以及制造电荷阱半导体存储器件的方法。 该方法包括：（a）在要沉积的半导体衬底的表面上涂覆第一前体材料并氧化第一前体材料以形成由绝缘材料形成的第一层; （b）在第一层上涂覆由金属性形成的第二前体材料; （c）在涂覆有第二前体材料的表面上提供第一前体材料以用第一前体材料代替第二前体材料; 和（d）氧化由（c）中得到的第一和第二前体材料以形成由绝缘材料和金属杂质形成的第二层，并且（a）至（d）至少进行一次以形成电荷阱 具有金属杂质在绝缘材料中隔离的结构的层。

    Nonvolatile semiconductor memory device and method of manufacturing the same
    48.
    发明申请
    Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20080023744A1

    公开(公告)日：2008-01-31

    申请号：US11723081

    申请日：2007-03-16

    Applicant: Sang-min Shin ,  Kwang-soo Seol ,  Young-gu Jin

    Inventor： Sang-min Shin ,  Kwang-soo Seol ,  Young-gu Jin

    IPC: H01L29/94

    CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/7881

    Abstract: Provided are a nonvolatile semiconductor memory device and a method of manufacturing the same. The nonvolatile semiconductor memory device may include a tunnel insulating layer formed on a semiconductor substrate, a charge trap layer including a dielectric layer doped with a transition metal formed on the tunnel insulating layer, a blocking insulating layer formed on the charge trap layer, and a gate electrode formed on the blocking insulating layer. The dielectric layer may be a high-k dielectric layer, for example, a HfO2 layer. Thus, the data retention characteristics of the nonvolatile semiconductor memory device may be improved because a deeper charge trap may be formed by doping the high-k dielectric layer with a transition metal.

    Abstract translation: 提供一种非易失性半导体存储器件及其制造方法。 非易失性半导体存储器件可以包括形成在半导体衬底上的隧道绝缘层，包含掺杂在隧道绝缘层上形成的过渡金属的电介质层的电荷陷阱层，形成在电荷陷阱层上的阻挡绝缘层，以及 栅电极形成在阻挡绝缘层上。 介电层可以是高k电介质层，例如HfO 2层。 因此，可以通过用过渡金属掺杂高k电介质层来形成更深的电荷陷阱来提高非易失性半导体存储器件的数据保持特性。

    Memory device and method of manufacturing the same
    49.
    发明申请
    Memory device and method of manufacturing the same 审中-公开
    存储器件及其制造方法

    公开(公告)号：US20070202648A1

    公开(公告)日：2007-08-30

    申请号：US11652583

    申请日：2007-01-12

    Applicant: Seong Jae Choi ,  Kwang Soo Seol ,  Jae-Young Choi ,  Dong-Kee Yi ,  Seon Mi Yoon

    Inventor： Seong Jae Choi ,  Kwang Soo Seol ,  Jae-Young Choi ,  Dong-Kee Yi ,  Seon Mi Yoon

    IPC: H01L21/336

    CPC classification number: B82Y10/00 ,  H01L29/40114

    Abstract: Provided is a memory device comprising a substrate, a source region, and a drain region that may be formed in the substrate and spaced apart from each other, a memory cell that may be formed on the surface of the substrate, connecting the source region and the drain region, and including a plurality of nanocrystals, wherein the memory cell comprises a first tunneling oxide layer formed on the substrate, and a control oxide layer including a plurality of nanocrystals formed on the tunneling oxide layer and a control gate formed on the memory cell. The memory device may include a polyelectrolyte film which enables a uniform arrangement of nanocrystals. The device characteristics may be controlled and a memory device with improved device characteristics may be provided.

    Abstract translation: 提供了一种存储器件，其包括可以形成在衬底中并彼此间隔开的衬底，源区和漏区，可以形成在衬底的表面上的存储单元，连接源区和 漏极区域，并且包括多个纳米晶体，其中所述存储单元包括形成在所述衬底上的第一隧道氧化物层，以及包括形成在所述隧道氧化物层上的多个纳米晶体的控制氧化物层和形成在所述存储器上的控制栅极 细胞。 存储器件可以包括能够均匀排列纳米晶体的聚电解质膜。 可以控制器件特性，并且可以提供具有改进的器件特性的存储器件。

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