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132 条记录 (耗时 0.018 秒)

    Output buffer for high and low voltage bus
    41.
    发明授权
    Output buffer for high and low voltage bus 失效
    高压和低压母线的输出缓冲器

    公开(公告)号：US06903581B2

    公开(公告)日：2005-06-07

    申请号：US10305530

    申请日：2002-11-26

    申请人： Lawrence T. Clark ,  Thomas J. Mozdzen

    发明人： Lawrence T. Clark ,  Thomas J. Mozdzen

    IPC分类号： G06F3/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K3/00

    CPC分类号： H03K19/018585

    摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the circuit configurations. The respective circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.

    摘要翻译： 简而言之，根据本发明的一个实施例，集成电路包括：输出缓冲器。 输出缓冲器包括耦合以提供电路配置的半导体器件。 输出缓冲器适于耦合到单独的电压电源电平端口，并且还适于在电路配置之间切换。 相应的电路配置分别专门用于与其他集成电路芯片互操作，不同的其他集成电路芯片的半导体器件的相应阈值电压电平是不同的。

    Digital regulation circuit
    42.
    发明授权
    Digital regulation circuit 有权

    公开(公告)号：US06801470B2

    公开(公告)日：2004-10-05

    申请号：US10329125

    申请日：2002-12-23

    申请人： Lawrence T. Clark ,  Neil F. Duetscher

    发明人： Lawrence T. Clark ,  Neil F. Duetscher

    IPC分类号： G11C700

    CPC分类号： G05F1/56

    摘要： A self-adjusting circuit provides a reverse body bias to circuitry in a DROWSY mode. Memory cells having the appropriate skews are supplied with a changing operating voltage potential, causing a memory cell to fail and determining the correct back bias potential VSS to supply that improves operation of the processor in a low power standby mode.

    Method and apparatus for increasing retention time in image sensors having an electronic shutter
    45.
    发明授权
    Method and apparatus for increasing retention time in image sensors having an electronic shutter 失效
    用于增加具有电子快门的图像传感器中的保留时间的方法和装置

    公开(公告)号：US06522357B2

    公开(公告)日：2003-02-18

    申请号：US08939808

    申请日：1997-09-30

    申请人： Mark A. Beiley ,  Eric J. Hoffman ,  Lawrence T. Clark

    发明人： Mark A. Beiley ,  Eric J. Hoffman ,  Lawrence T. Clark

    IPC分类号： H04N314

    CPC分类号： H04N5/3595 ,  H04N5/353

    摘要： In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.

    摘要翻译： 在具有电子快门的像素中，公开了增加电子快门的保持时间的方法。 采用复位信号，在集成完成后立即将二极管节点驱动到预定电压。 采样信号用于控制通过门。 采样信号包括采样信号为负电压的状态。

    Secure true random number generation using 1.5-T transistor flash memory
    48.
    发明授权
    Secure true random number generation using 1.5-T transistor flash memory 有权

    公开(公告)号：US10078494B2

    公开(公告)日：2018-09-18

    申请号：US15276087

    申请日：2016-09-26

    申请人： Lawrence T. Clark ,  James Adams ,  Keith E. Holbert

    发明人： Lawrence T. Clark ,  James Adams ,  Keith E. Holbert

    IPC分类号： G06F7/58

    CPC分类号： G06F7/588

    摘要： This disclosure relates generally to physically unclonable function (PUF) circuitry along with methods of generating numbers. In one embodiment, the PUF circuitry includes a memory, a memory control circuitry, and whitening circuitry. To reduce or eliminate the systematic bias from the array, whitening circuitry is configured to generate a random number comprising random number bits in response to the memory control circuit implementing at least one sequence of memory cycles on the array of the memory cells in the memory. The whitening circuitry is configured to provide the random number bits of the random number based on the variable bit states stored by the array of the memory cells. On average the whitening circuitry is configured to provide approximately half of the random number bits in the first bit state and half of random number bits in a second bit state.

    Low complexity out-of-order issue logic using static circuits
    49.
    发明授权
    Low complexity out-of-order issue logic using static circuits 有权

    公开(公告)号：US09740494B2

    公开(公告)日：2017-08-22

    申请号：US13459964

    申请日：2012-04-30

    申请人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    发明人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3851

    摘要： Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.