公开(公告)号：US20220093822A1

公开(公告)日：2022-03-24

申请号：US17415574

申请日：2019-12-26

Applicant: Soitec

Inventor： Mariia Rozhavskaia

IPC: H01L33/06 ,  H01L33/00 ,  H01L33/12

Abstract: An optoelectronic semiconductor structure (SC) comprises an active InGaN-based layer disposed between an n-type injection layer and a p-type injection layer, the active p-type injection layer comprising a first InGaN layer and, disposed on the first layer, a second layer composed of a plurality of Al—GaInN elemental layers, each elemental layer having a thickness less than its critical relaxation thickness, two successive elemental layers having different aluminum and/or indium and/or gallium compositions.

公开(公告)号：US20220073343A1

公开(公告)日：2022-03-10

申请号：US17416368

申请日：2019-12-12

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: B81C1/00

Abstract: A method for transferring a superficial layer to a carrier substrate having cavities comprises: —providing a donor substrate, —providing the carrier substrate having a first face and comprising cavities, each cavity opening at the first face and having a bottom and peripheral walls, —creating at least one temporary pillar in at least one of the cavities, the pillar having an upper surface that is coplanar with the first face of the carrier substrate, joining the donor substrate and the carrier substrate at the first face of the carrier substrate, —thinning the donor substrate to form the superficial layer, and removing the at least one temporary pillar.

公开(公告)号：US11245050B2

公开(公告)日：2022-02-08

申请号：US16487037

申请日：2018-02-26

Applicant: Soitec

Inventor： David Sotta

IPC: H01L33/12 ,  H01L33/00 ,  H01L21/02 ,  H01L21/324

Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.

公开(公告)号：US20210407849A1

公开(公告)日：2021-12-30

申请号：US17414858

申请日：2020-01-08

Applicant: Soitec

Inventor： Marcel Broekaart ,  Damien Parissi

IPC: H01L21/762 ,  H01L21/02

Abstract: A process for producing a receiver substrate for a semiconductor-on-insulator structure for radiofrequency application comprises the following steps: providing a semiconductor substrate comprising a base substrate made of monocrystalline material and a charge-trapping layer made of polycrystalline silicon arranged on the base substrate; oxidizing the charge-trapping layer to form an oxide layer arranged on the charge-trapping layer. The oxidation of the charge-trapping layer is performed at least partly at a temperature lower than or equal to 875° C., in the following manner: starting the oxidization at a first temperature (T1) between 750° C. and 1000° C.; decreasing the temperature down to a second temperature (T2), lower than the first temperature (T1), between 750° C. and 875° C.; continuing the oxidization at the second temperature (T2).

公开(公告)号：US20210384223A1

公开(公告)日：2021-12-09

申请号：US17254808

申请日：2019-06-21

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Manuel Sellier ,  Ludovic Ecarnot

IPC: H01L27/12 ,  H01L27/146

Abstract: The invention relates to a front-side imager comprising in succession: —a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises between the carrier substrate and the first electrically insulating layer: —a second electrically insulating separating layer, and —a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.

公开(公告)号：US20210351318A1

公开(公告)日：2021-11-11

申请号：US17385138

申请日：2021-07-26

Applicant: Soitec

Inventor： David Sotta

IPC: H01L33/00 ,  H01L21/02 ,  H01L21/324 ,  H01L33/12

Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.

公开(公告)号：US11081521B2

公开(公告)日：2021-08-03

申请号：US16352085

申请日：2019-03-13

Applicant: Soitec

Inventor： Jean-Marc Bethoux

IPC: H01L27/15 ,  H01L33/00 ,  H01L33/32 ,  H01L33/06 ,  H01L33/12 ,  H01L21/02 ,  H01L25/075 ,  H01L33/02

Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having different lattice parameters includes providing a relaxation substrate comprising a support and a flow layer on the support that includes first and second groups of blocks having different viscosities at a relaxation temperature. The relaxation substrate also comprises a plurality of strained crystalline semiconductor islands on the flow layer, the islands of a first group being located on the first group of blocks and islands of a second group being located on the second group of blocks. The relaxation substrate is then heat treated at a relaxation temperature higher than or equal to the glass transition temperature of at least one block of the flow layer to cause differentiated lateral expansion of the first and second groups of islands such that the first and second groups of relaxed islands then have different lattice parameters.

公开(公告)号：US20210132002A1

公开(公告)日：2021-05-06

申请号：US17044205

申请日：2019-03-19

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: G01N27/414 ,  H01L21/306 ,  H01L21/762 ,  B01L3/00

Abstract: A microsensor for detecting ions in a fluid, comprises: a field-effect transistor having a source, a drain, an active region between the source and the drain, and a gate disposed above the active region, an active layer, in which the active region is formed, a dielectric layer positioned beneath the active layer, a support substrate disposed under the dielectric layer and comprising at least one buried cavity located plumb with the gate of the field-effect transistor in order to receive the fluid.

公开(公告)号：US20210058058A1

公开(公告)日：2021-02-25

申请号：US17075465

申请日：2020-10-20

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H03H3/10

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US20210054528A1

公开(公告)日：2021-02-25

申请号：US17042699

申请日：2019-03-26

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: C30B29/32 ,  H01L21/02 ,  H01L21/762 ,  C30B29/42 ,  C30B25/18 ,  C30B23/02

Abstract: A process for producing a monocrystalline layer of GaAs material comprises the transfer of a monocrystalline seed layer of SrTiO3 material to a carrier substrate of silicon material followed by epitaxial growth of a monocrystalline layer of GaAs material.