公开(公告)号：US10771048B2

公开(公告)日：2020-09-08

申请号：US16747341

申请日：2020-01-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Capucine Lecat-Mathieu De Boissac ,  Fady Abouzeid ,  Gilles Gasiot ,  Philippe Roche ,  Victor Malherbe

IPC: H03K5/14 ,  H03K5/135 ,  H03K5/00

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

公开(公告)号：US20200212927A1

公开(公告)日：2020-07-02

申请号：US16709391

申请日：2019-12-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Alps) SAS

Inventor： Stephane LE TUAL ,  Jean-Pierre BLANC ,  David DUPERRAY

IPC: H03M1/68 ,  H03M1/06

Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.

公开(公告)号：US20200184110A1

公开(公告)日：2020-06-11

申请号：US16213500

申请日：2018-12-07

Applicant: STMicroelectronics SA ,  INSTITUT POLYTECHNIQUE DE GRENOBLE

Inventor： Sophie Germain ,  Sylvain Engels ,  Laurent Fesquet

IPC: G06F21/72 ,  G06F21/75 ,  G06F21/60 ,  G06F21/77 ,  H03K5/14

Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.

公开(公告)号：US10659034B2

公开(公告)日：2020-05-19

申请号：US16429544

申请日：2019-06-03

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Renan Lethiecq

IPC: H03K17/687 ,  H03K17/14 ,  H03K3/356 ,  H01L27/12

Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.

公开(公告)号：US10607949B2

公开(公告)日：2020-03-31

申请号：US15607780

申请日：2017-05-30

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics SA

Inventor： Yves Mazoyer ,  Philippe Galy ,  Philippe Sirito-Olivier

IPC: H01L23/60 ,  H01L23/62 ,  H01L27/02

Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.

公开(公告)号：US10585143B2

公开(公告)日：2020-03-10

申请号：US16031960

申请日：2018-07-10

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Pascal Urard ,  Florian Cacho ,  Vincent Huard ,  Alok Kumar Tripathi

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3181 ,  G06F17/50

Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.

公开(公告)号：US20200006320A1

公开(公告)日：2020-01-02

申请号：US16454230

申请日：2019-06-27

Applicant: STMicroelectronics SA

Inventor： Thomas BEDECARRATS ,  Louise DE CONTI ,  Philippe GALY

IPC: H01L27/02

Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.

公开(公告)号：US10469124B2

公开(公告)日：2019-11-05

申请号：US15968927

申请日：2018-05-02

Applicant: STMicroelectronics SA

Inventor： Laurent Chabert ,  Raphael Paulin

IPC: H04B1/48 ,  H04B1/16 ,  H04B1/18 ,  H03F3/195 ,  H03F1/26 ,  H03F1/52 ,  H03F3/72

Abstract: A communications device includes a transmission chain coupled to an antenna a receiver chain coupled to the antenna. The receiver chain includes an amplifier device having an input coupled to the antenna. A controlled switching circuit is included in the amplifier device and is operable to selectively disconnect conduction terminals of an amplifying transistor from power supply terminals when the transmission chain is operating to pass a transmit signal to the antenna.

公开(公告)号：US10455123B2

公开(公告)日：2019-10-22

申请号：US15591597

申请日：2017-05-10

Applicant: STMicroelectronics SA

Inventor： Estelle Lesellier

IPC: H04N1/60 ,  G06T5/00 ,  G06T5/40 ,  H04N1/62

Abstract: An image formed from pixels each having components defining a color is processed to implement an increase in the saturation of the image depending on a gain applied by a transfer function depending on the components of the color of each pixel. The gain of the transfer function is parameterized using at least one control parameter respectively dedicated to at least one type of reference image content. The value of the at least one control parameter is calculated depending on the actual content of the image by implementing calculations including determining colorimetric statistics of the pixels of the image and processing the statistics in accordance with at least one processing model respectively associated with the at least one type of reference image content.

公开(公告)号：US10395383B2

公开(公告)日：2019-08-27

申请号：US15381928

申请日：2016-12-16

Applicant: STMicroelectronics SA

Inventor： Manu Alibay ,  Stéphane Auberger ,  Bogdan-Florin Stanciulescu

IPC: G06K9/00 ,  G06T7/70

Abstract: A method estimates an ego-motion of an apparatus between a first image and a second image of a succession of images captured by the apparatus, in a SLAM type algorithm containing a localization part including the ego-motion estimating and a mapping part. The ego-motion comprises a 3D rotation of the apparatus and a position variation of the apparatus in the 3D space, and the ego-motion estimating comprises performing a first part and performing a second part after having performed the first part, the first part including estimating the 3D rotation of the apparatus and the second part including, the 3D rotation having been estimated, estimating the position variation of the apparatus in the 3D space.