Method of making a reference current generator
    42.
    发明授权
    Method of making a reference current generator 失效
    制作参考电流发生器的方法

    公开(公告)号:US5686822A

    公开(公告)日:1997-11-11

    申请号:US640108

    申请日:1996-04-30

    IPC分类号: G05F3/26 G05F1/10

    CPC分类号: G05F3/265

    摘要: A current generator and method of making a current generator in which two resistors are provided, each in series with one of two transistors in the generator, and in which one of the resistors is trimmed if the reference current is too large and the other is trimmed if the reference current is too small, thereby obviating the problems of the prior art in which one resistor must be trimmed by a potentially large and unacceptable amount. The two resistors are formed with a distribution of resistances which is centered on their corresponding target resistance values so that the number of resistors to be trimmed and the amount of trimming per resistor are reduced. The appropriate target resistances of the resistors can be determined if a maximum trim factor is set. The method is insensitive to variations in the process by which the resistances of the resistors are initially set and reduces the variability of the untrimmed reference current with respect to resistor critical dimensions.

    摘要翻译: 一种电流发生器和制造电流发生器的方法,其中设置有两个电阻器,每个电阻器与发生器中的两个晶体管中的一个串联,并且如果参考电流太大而另一个被修整,则电阻器中的一个被修整 如果参考电流太小,从而避免了现有技术的问题,其中一个电阻器必须用可能大的和不可接受的量来修整。 两个电阻器形成有以其对应的目标电阻值为中心的电阻分布,使得要修整的电阻器的数量和每个电阻器的修整量减少。 如果设置了最大微调因子,则可以确定电阻器的适当目标电阻。 该方法对于最初设置电阻器的电阻的过程中的变化不敏感,并且减小未匹配参考电流相对于电阻器关键尺寸的可变性。

    SIGNAL CONVERTING APPARATUS AND RECEIVING APPARATUS FOR SUPPORTING CONCURRENT DUAL BANDS IN WIRELESS COMMUNICATION SYSTEM
    43.
    发明申请
    SIGNAL CONVERTING APPARATUS AND RECEIVING APPARATUS FOR SUPPORTING CONCURRENT DUAL BANDS IN WIRELESS COMMUNICATION SYSTEM 有权
    信号转换装置和接收装置,用于支持无线通信系统中的同步双卡

    公开(公告)号:US20130244606A1

    公开(公告)日:2013-09-19

    申请号:US13423685

    申请日:2012-03-19

    摘要: A receiving apparatus in a wireless communication system includes: an antenna configured to receive a wireless frequency signal including a first frequency band signal and a second frequency band signal; a low noise amplifier (LNA) configured to amplify the wireless frequency signal, output the first frequency band signal as a differential phase signal, and output the second frequency band signal as a common phase signal; a differentiator configured to pass only the differential phase signal between the signals outputted from the LNA; and a combiner configured to pass only the common phase signal between the signals outputted from the LNA.

    摘要翻译: 无线通信系统中的接收装置包括:天线,被配置为接收包括第一频带信号和第二频带信号的无线频率信号; 配置为放大无线频率信号的低噪声放大器(LNA),将第一频带信号输出为差分相位信号,并输出第二频带信号作为公共相位信号; 一个微分器,被配置为仅在所述LNA输出的信号之间通过所述差分相位信号; 以及组合器,其被配置为仅在从LNA输出的信号之间传递公共相位信号。

    Wake-up receiver and wake-up method using duty cycling and power off technique
    44.
    发明授权
    Wake-up receiver and wake-up method using duty cycling and power off technique 有权
    唤醒接收机和唤醒方式,使用负载循环和关机技术

    公开(公告)号:US08285243B2

    公开(公告)日:2012-10-09

    申请号:US12808766

    申请日:2008-12-03

    IPC分类号: H04B1/16

    摘要: Provided is a low-power wake-up receiver that is sensitive to electric waves, by which power consumed by a radio frequency (RF) transceiver of a sensor node in a ubiquitous sensor network (USN) is minimized. A wake-up receiver waking up a main transceiver includes a duty cycle signal generation unit controlling a duty cycle of a duty cycle signal; a burst signal detection unit receiving an input signal including a burst signal and a data signal based on the duty cycle signal, amplifying the input signal, and, if the amplified input signal is the burst signal, outputting a control signal; and a data signal detection unit re-amplifying the amplified input signal based on the control signal, and, if the re-amplified input signal is the data signal, outputting a wake-up signal. Power supplied to the duty cycle signal generation unit is interrupted based on the control signal and power is re-supplied to the duty cycle signal generation unit based on the wake-up signal.

    摘要翻译: 提供了一种对电波敏感的低功率唤醒接收机,通过这种接收器可以最小化无处不在的传感器网络(USN)中的传感器节点的射频(RF)收发器所消耗的功率。 唤醒主收发器的唤醒接收机包括:占空比信号发生单元,控制占空比信号的占空比; 突发信号检测单元,基于占空比信号接收包括脉冲串信号和数据信号的输入信号,放大输入信号,如果放大的输入信号是脉冲串信号,则输出控制信号; 并且数据信号检测单元基于控制信号对放大的输入信号进行再放大,并且如果再放大的输入信号是数据信号,则输出唤醒信号。 基于该控制信号,中断向占空比信号生成部供给的电力,并根据该唤醒信号将功率重新提供给占空比信号生成部。

    DC offset cancellation circuit
    45.
    发明授权
    DC offset cancellation circuit 有权
    DC偏移消除电路

    公开(公告)号:US08222944B2

    公开(公告)日:2012-07-17

    申请号:US12950193

    申请日:2010-11-19

    IPC分类号: H03L5/00

    摘要: A DC offset cancellation circuit includes: a control signal generation unit generating i (i is a natural number) number of pulse signals having a pulse width corresponding to a DC offset amount; a current source supplying i number of currents each having a different current ratio; a switching unit determining a current quantity to be supplied to a feedback capacitor by adjusting a turn-on quantity of each of the i number of currents according to the pulse width of each of the i number of pulse signals; and an electric charge quantity regulation unit charging DC offset electric charges corresponding to current supplied from the switching unit through the feedback capacitor and transferring the DC offset electric charges charged in the feedback capacitor to a sampling capacitor through a rotary capacitor, to allow the sampling capacitor to primarily store the DC offset electric charges and then secondarily store electric charges corresponding to an input signal.

    摘要翻译: DC偏移消除电路包括:控制信号生成单元,生成具有对应于DC偏移量的脉冲宽度的i(i是自然数)个脉冲信号; 电流源,其提供i个具有不同电流比的电流; 切换单元,根据i个脉冲信号中的每一个的脉冲宽度,调整i个电流的导通量,确定要提供给反馈电容器的电流量; 电荷量调节单元对通过反馈电容器从开关单元提供的电流充电DC偏移电荷,并将通过旋转电容器将充电在反馈电容器中的DC偏移电荷传送到采样电容器,以允许采样电容器 主要存储DC偏移电荷,然后二次存储对应于输入信号的电荷。

    Digital feedforward sigma-delta modulator in analog-to-digital converter and modulation method thereof
    46.
    发明授权
    Digital feedforward sigma-delta modulator in analog-to-digital converter and modulation method thereof 有权
    数模转换器中的数字前馈Σ-Δ调制器及其调制方法

    公开(公告)号:US08120518B2

    公开(公告)日:2012-02-21

    申请号:US12814533

    申请日:2010-06-14

    IPC分类号: H03M3/00

    CPC分类号: H03M3/42 H03M3/452

    摘要: A digital feedforward sigma-delta modulator in an analog-to-digital converter and its modulation method are disclosed. The modulator changes a feedforward path from an analog domain to a digital domain and processes it. The modulator integrates an analog input by using a plurality of integrators, weights them, quantizes them by using a plurality of quantizers in a digital domain to output digital signals, and then adds up the thusly outputted digital signals by using a digital adder. In case of a continuous time digital feedforward sigma-delta modulator (SDM), a digital signal outputted from the digital adder is weighted and then immediately inputted to the digital adder in the digital domain so as to be subtracted, allowing for digital feedforwarding. Because the feedforward signal is processed in the digital domain, the area occupied by an analog circuit and power consumption can be reduced. Also, because signals are added up in the digital domain, a digital output signal can be immediately used when an excess loop delay needs to be corrected. Thus, because there is no need to convert the digital output signal into an analog signal by using a DAC, the DAC can be omitted.

    摘要翻译: 公开了一种模拟数字转换器中的数字前馈Σ-Δ调制器及其调制方法。 调制器改变从模拟域到数字域的前馈路径并处理它。 调制器通过使用多个积分器对模拟输入进行积分,对它们进行加权,通过使用数字域中的多个量化器量化它们以输出数字信号,然后通过使用数字加法器将所输出的数字信号相加。 在连续时间数字前馈Σ-Δ调制器(SDM)的情况下,从数字加法器输出的数字信号被加权,然后在数字域中立即输入到数字加法器,以便减去数字前馈。 由于前馈信号在数字域中被处理,所以可以减少由模拟电路占用的面积和功耗。 另外,由于信号在数字域中相加,所以当需要纠正多余的环路延迟时,可以立即使用数字输出信号。 因此,由于不需要通过使用DAC将数字输出信号转换为模拟信号,所以可以省略DAC。

    DIGITAL-TO-ANALOG CONVERTER CIRCUIT USING CHARGE SUBTRACTION METHOD AND CHARGE TRANSFER INTERPOLATION METHOD
    47.
    发明申请
    DIGITAL-TO-ANALOG CONVERTER CIRCUIT USING CHARGE SUBTRACTION METHOD AND CHARGE TRANSFER INTERPOLATION METHOD 审中-公开
    使用电荷分析方法和电荷转移插值方法的数字到模拟转换器电路

    公开(公告)号:US20110279298A1

    公开(公告)日:2011-11-17

    申请号:US13100596

    申请日:2011-05-04

    IPC分类号: H03M1/66

    CPC分类号: H03M1/68 H03M1/765 H03M1/804

    摘要: A DAC circuit using a charge subtraction method and a change transfer interpolation method includes resistor cells configured to divide a voltage of data of total K bits (=upper M bits+lower N bits) by resistance dividers; a decoder group configured to receive digital data of the M bits and the N bits divided in the resistor cells, process the digital data by the unit of 2 bits, and output respective corresponding voltages; a capacitor group configured to receive the voltages outputted from the decoder group and realize charge charging by a charge subtraction method and charge transferring by a charge transfer interpolation method; and an operational amplifier having a first input terminal which receives a reference voltage and a second input terminal which receives an interpolation voltage corresponding to an amount of charges transferred from the capacitor group, and configured to generate an output voltage.

    摘要翻译: 使用电荷减法和变迁内插法的DAC电路包括电阻单元,其被配置为通过电阻分压器来分配总共K位(=高M位+低N位)的数据的电压; 配置为接收M位的数字数据和在电阻单元中划分的N位的解码器组,以2位为单位处理数字数据,并输出相应的对应电压; 电容器组,被配置为接收从解码器组输出的电压,并通过电荷减法方法实现充电充电,并通过电荷转移插值方法进行电荷转移; 以及运算放大器,其具有接收参考电压的第一输入端子和接收与从所述电容器组传送的电荷量对应的内插电压的第二输入端子,并且被配置为产生输出电压。

    APPARATUS FOR REJECTING IMAGE IN RECEIVER
    48.
    发明申请
    APPARATUS FOR REJECTING IMAGE IN RECEIVER 失效
    用于拒绝接收器中的图像的装置

    公开(公告)号:US20110182388A1

    公开(公告)日:2011-07-28

    申请号:US12695860

    申请日:2010-01-28

    IPC分类号: H04L27/08

    摘要: The present invention relates to an apparatus for rejecting images in a receiver.The apparatus of the present invention relates to an apparatus for rejecting image signals in a receiver of a direct conversion structure and comprises a signal mismatch compensation unit configured to detect gain error and phase error between an In-phase (I) signal and a Quadrature (Q) signal received through the receiver, to reject image signals existing in the I and Q signals, and to output a result. The signal mismatch compensation unit detects the gain error and the phase error using an adaptive step method of reducing the step size of the gain error and the phase error step by step whenever the gain error and the phase error are converged.According to the present invention, high image rejection ratio is achieved and the adaptation time taken to obtain a high image rejection ratio is reduced simultaneously. Further, a bad influence of the DC offset on the image rejection ratio can be prevented by removing DC offset signals in a digital structure, accordingly, error can be accurately estimated.

    摘要翻译: 本发明涉及一种用于拒绝接收机中的图像的装置。 本发明的装置涉及一种用于拒绝直接转换结构的接收机中的图像信号的装置,并且包括:信号失配补偿单元,被配置为检测同相(I)信号和正交(I)信号之间的增益误差和相位误差, Q)信号,以消除存在于I和Q信号中的图像信号,并输出结果。 信号失配补偿单元使用自适应步长法,在增益误差和相位误差收敛的情况下逐步减小增益误差的步长和相位误差来检测增益误差和相位误差。 根据本发明,实现了高的图像抑制比,同时降低了获得高的图像抑制比所需的适应时间。 此外,通过去除数字结构中的DC偏移信号,可以防止DC偏移对图像抑制比的不良影响,因此可以准确地估计误差。

    WAKE-UP RECEIVER AND WAKE-UP METHOD USING DUTY CYCLING AND POWER OFF TECHNIQUE
    49.
    发明申请
    WAKE-UP RECEIVER AND WAKE-UP METHOD USING DUTY CYCLING AND POWER OFF TECHNIQUE 有权
    唤醒接收器和唤醒方法使用占空比和关机技术

    公开(公告)号:US20110006824A1

    公开(公告)日:2011-01-13

    申请号:US12808766

    申请日:2008-12-03

    IPC分类号: H03K3/017

    摘要: Provided is a low-power wake-up receiver that is sensitive to electric waves, by which power consumed by a radio frequency (RF) transceiver of a sensor node in a ubiquitous sensor network (USN) is minimized. A wake-up receiver waking up a main transceiver includes a duty cycle signal generation unit controlling a duty cycle of a duty cycle signal; a burst signal detection unit receiving an input signal including a burst signal and a data signal based on the duty cycle signal, amplifying the input signal, and, if the amplified input signal is the burst signal, outputting a control signal; and a data signal detection unit re-amplifying the amplified input signal based on the control signal, and, if the re-amplified input signal is the data signal, outputting a wake-up signal. Power supplied to the duty cycle signal generation unit is interrupted based on the control signal and power is re-supplied to the duty cycle signal generation unit based on the wake-up signal.

    摘要翻译: 提供了一种对电波敏感的低功率唤醒接收机,通过这种接收器可以最小化无处不在的传感器网络(USN)中的传感器节点的射频(RF)收发器所消耗的功率。 唤醒主收发器的唤醒接收机包括:占空比信号发生单元,控制占空比信号的占空比; 突发信号检测单元,基于占空比信号接收包括脉冲串信号和数据信号的输入信号,放大输入信号,如果放大的输入信号是脉冲串信号,则输出控制信号; 并且数据信号检测单元基于控制信号对放大的输入信号进行再放大,并且如果再放大的输入信号是数据信号,则输出唤醒信号。 基于该控制信号,中断向占空比信号生成部供给的电力,并根据该唤醒信号将功率重新提供给占空比信号生成部。

    GM-BOOSTED DIFFERENTIAL DRAIN-TO-SOURCE FEEDBACK COLPITTS VOLTAGE CONTROLLED OSCILLATOR
    50.
    发明申请
    GM-BOOSTED DIFFERENTIAL DRAIN-TO-SOURCE FEEDBACK COLPITTS VOLTAGE CONTROLLED OSCILLATOR 失效
    GM-BOOSTED差分漏极反馈反馈电压电压控制振荡器

    公开(公告)号:US20100289592A1

    公开(公告)日:2010-11-18

    申请号:US12690136

    申请日:2010-01-20

    IPC分类号: H03B5/12

    摘要: A voltage controlled oscillator outputting a differential signal includes: an inductor connected to a first power supply supplying first voltage; first and second transistors for differential switching; first and second variable capacitors connected to the inductor in parallel; a third transistor of which a gate electrode is connected to a first node; and a fourth transistor of which a gate electrode is connected to a second node. When bias voltage is applied to the gate electrode of the first transistor to be turned on, negative resistance is generated by voltage applied to the first capacitor and the second capacitor through the first transistor. When voltage outputted through the first node is applied to the gate electrode of the third transistor to be turned on, the voltage is additionally applied to the first capacitor and the second capacitor by the third transistor to increase the negative resistance.

    摘要翻译: 输出差分信号的压控振荡器包括:电感器,连接到提供第一电压的第一电源; 用于差分开关的第一和第二晶体管; 并联连接到电感器的第一和第二可变电容器; 栅电极连接到第一节点的第三晶体管; 以及栅电极连接到第二节点的第四晶体管。 当偏置电压施加到要导通的第一晶体管的栅电极时,通过第一晶体管施加到第一电容器和第二电容器的电压产生负电阻。 当通过第一节点输出的电压被施加到要导通的第三晶体管的栅电极时,由第三晶体管将电压附加到第一电容器和第二电容器以增加负电阻。