摘要:
An apparatus and method for converting a frequency of a high frequency signal received from an antenna in an ultra wide band communication system transmitting and receiving using at least two reference frequencies. The method includes generating generation frequencies having frequencies set to convert the frequency of the high frequency signal and mixing the frequency of the high frequency signal and the generation frequencies in at least two stages.
摘要:
A current generator and method of making a current generator in which two resistors are provided, each in series with one of two transistors in the generator, and in which one of the resistors is trimmed if the reference current is too large and the other is trimmed if the reference current is too small, thereby obviating the problems of the prior art in which one resistor must be trimmed by a potentially large and unacceptable amount. The two resistors are formed with a distribution of resistances which is centered on their corresponding target resistance values so that the number of resistors to be trimmed and the amount of trimming per resistor are reduced. The appropriate target resistances of the resistors can be determined if a maximum trim factor is set. The method is insensitive to variations in the process by which the resistances of the resistors are initially set and reduces the variability of the untrimmed reference current with respect to resistor critical dimensions.
摘要:
A receiving apparatus in a wireless communication system includes: an antenna configured to receive a wireless frequency signal including a first frequency band signal and a second frequency band signal; a low noise amplifier (LNA) configured to amplify the wireless frequency signal, output the first frequency band signal as a differential phase signal, and output the second frequency band signal as a common phase signal; a differentiator configured to pass only the differential phase signal between the signals outputted from the LNA; and a combiner configured to pass only the common phase signal between the signals outputted from the LNA.
摘要:
Provided is a low-power wake-up receiver that is sensitive to electric waves, by which power consumed by a radio frequency (RF) transceiver of a sensor node in a ubiquitous sensor network (USN) is minimized. A wake-up receiver waking up a main transceiver includes a duty cycle signal generation unit controlling a duty cycle of a duty cycle signal; a burst signal detection unit receiving an input signal including a burst signal and a data signal based on the duty cycle signal, amplifying the input signal, and, if the amplified input signal is the burst signal, outputting a control signal; and a data signal detection unit re-amplifying the amplified input signal based on the control signal, and, if the re-amplified input signal is the data signal, outputting a wake-up signal. Power supplied to the duty cycle signal generation unit is interrupted based on the control signal and power is re-supplied to the duty cycle signal generation unit based on the wake-up signal.
摘要:
A DC offset cancellation circuit includes: a control signal generation unit generating i (i is a natural number) number of pulse signals having a pulse width corresponding to a DC offset amount; a current source supplying i number of currents each having a different current ratio; a switching unit determining a current quantity to be supplied to a feedback capacitor by adjusting a turn-on quantity of each of the i number of currents according to the pulse width of each of the i number of pulse signals; and an electric charge quantity regulation unit charging DC offset electric charges corresponding to current supplied from the switching unit through the feedback capacitor and transferring the DC offset electric charges charged in the feedback capacitor to a sampling capacitor through a rotary capacitor, to allow the sampling capacitor to primarily store the DC offset electric charges and then secondarily store electric charges corresponding to an input signal.
摘要:
A digital feedforward sigma-delta modulator in an analog-to-digital converter and its modulation method are disclosed. The modulator changes a feedforward path from an analog domain to a digital domain and processes it. The modulator integrates an analog input by using a plurality of integrators, weights them, quantizes them by using a plurality of quantizers in a digital domain to output digital signals, and then adds up the thusly outputted digital signals by using a digital adder. In case of a continuous time digital feedforward sigma-delta modulator (SDM), a digital signal outputted from the digital adder is weighted and then immediately inputted to the digital adder in the digital domain so as to be subtracted, allowing for digital feedforwarding. Because the feedforward signal is processed in the digital domain, the area occupied by an analog circuit and power consumption can be reduced. Also, because signals are added up in the digital domain, a digital output signal can be immediately used when an excess loop delay needs to be corrected. Thus, because there is no need to convert the digital output signal into an analog signal by using a DAC, the DAC can be omitted.
摘要:
A DAC circuit using a charge subtraction method and a change transfer interpolation method includes resistor cells configured to divide a voltage of data of total K bits (=upper M bits+lower N bits) by resistance dividers; a decoder group configured to receive digital data of the M bits and the N bits divided in the resistor cells, process the digital data by the unit of 2 bits, and output respective corresponding voltages; a capacitor group configured to receive the voltages outputted from the decoder group and realize charge charging by a charge subtraction method and charge transferring by a charge transfer interpolation method; and an operational amplifier having a first input terminal which receives a reference voltage and a second input terminal which receives an interpolation voltage corresponding to an amount of charges transferred from the capacitor group, and configured to generate an output voltage.
摘要:
The present invention relates to an apparatus for rejecting images in a receiver.The apparatus of the present invention relates to an apparatus for rejecting image signals in a receiver of a direct conversion structure and comprises a signal mismatch compensation unit configured to detect gain error and phase error between an In-phase (I) signal and a Quadrature (Q) signal received through the receiver, to reject image signals existing in the I and Q signals, and to output a result. The signal mismatch compensation unit detects the gain error and the phase error using an adaptive step method of reducing the step size of the gain error and the phase error step by step whenever the gain error and the phase error are converged.According to the present invention, high image rejection ratio is achieved and the adaptation time taken to obtain a high image rejection ratio is reduced simultaneously. Further, a bad influence of the DC offset on the image rejection ratio can be prevented by removing DC offset signals in a digital structure, accordingly, error can be accurately estimated.
摘要:
Provided is a low-power wake-up receiver that is sensitive to electric waves, by which power consumed by a radio frequency (RF) transceiver of a sensor node in a ubiquitous sensor network (USN) is minimized. A wake-up receiver waking up a main transceiver includes a duty cycle signal generation unit controlling a duty cycle of a duty cycle signal; a burst signal detection unit receiving an input signal including a burst signal and a data signal based on the duty cycle signal, amplifying the input signal, and, if the amplified input signal is the burst signal, outputting a control signal; and a data signal detection unit re-amplifying the amplified input signal based on the control signal, and, if the re-amplified input signal is the data signal, outputting a wake-up signal. Power supplied to the duty cycle signal generation unit is interrupted based on the control signal and power is re-supplied to the duty cycle signal generation unit based on the wake-up signal.
摘要:
A voltage controlled oscillator outputting a differential signal includes: an inductor connected to a first power supply supplying first voltage; first and second transistors for differential switching; first and second variable capacitors connected to the inductor in parallel; a third transistor of which a gate electrode is connected to a first node; and a fourth transistor of which a gate electrode is connected to a second node. When bias voltage is applied to the gate electrode of the first transistor to be turned on, negative resistance is generated by voltage applied to the first capacitor and the second capacitor through the first transistor. When voltage outputted through the first node is applied to the gate electrode of the third transistor to be turned on, the voltage is additionally applied to the first capacitor and the second capacitor by the third transistor to increase the negative resistance.