公开(公告)号：US20080129717A1

公开(公告)日：2008-06-05

申请号：US11999329

申请日：2007-12-04

Applicant: Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-jin Jeon

Inventor： Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-jin Jeon

IPC: G06F3/038

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2320/0223

Abstract: In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Abstract translation: 在具有显示面板的显示面板和显示装置中，显示面板包括阵列和相对的基板。 阵列基板包括显示器和外围区域。 栅极和源极线形成在显示区域中。 在周边区域中形成栅极驱动部分和第一和第二时钟线。 栅极驱动部分将栅极信号输出到栅极线。 第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。 相对的衬底与阵列衬底组合并且包括公共电极层。 公共电极层具有图案化以暴露第一和第二时钟线的开口部分。 第一和第二时钟线的暴露部分具有基本上相同的面积。 因此，可以使门信号的延迟最小化并且可以防止门信号的失真。

公开(公告)号：US07320906B2

公开(公告)日：2008-01-22

申请号：US10922343

申请日：2004-08-19

Applicant: Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

Inventor： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

IPC: H01L21/84

CPC classification number: H01L29/41733 ,  H01L27/124

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US20070296885A1

公开(公告)日：2007-12-27

申请号：US11854059

申请日：2007-09-12

Applicant: Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

Inventor： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

IPC: H01L21/4763 ,  G02F1/136 ,  H01L23/52

CPC classification number: G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/66765

Abstract: A device and corresponding method of fabrication thereof are disclosed, where the device provides a contact for semiconductor and display devices, the device including a substrate, a first wiring line assembly formed on the substrate, an under-layer formed on the first wiring line assembly, an organic insulating layer formed on the under-layer such that the organic insulating layer covers the under-layer, a pattern on the organic insulating layer for contact holes to expose the under-layer, etched contact holes formed in the under-layer in correspondence with the pattern such that the underlying first wiring line assembly is exposed to the outside, a cured organic insulating layer formed on the under-layer, and a second wiring line assembly formed on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the etched contact holes, and the corresponding method of fabrication including forming a first wiring line assembly on a substrate, forming an under-layer on the first wiring line assembly, forming an organic insulating layer such that the organic insulating layer covers the under-layer patterning the organic insulating layer to thereby form contact holes exposing the under-layer, etching the under-layer exposed through the contact holes such that the underlying first wiring line assembly is exposed to the outside, curing the organic insulating layer, and forming a second wiring line assembly on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the contact holes.

Abstract translation: 公开了一种器件及其相应的制造方法，其中器件为半导体和显示器件提供接触，该器件包括衬底，形成在衬底上的第一布线组件，形成在第一布线组件上的底层 形成在下层上的有机绝缘层，使得有机绝缘层覆盖下层，在有机绝缘层上形成用于接触孔的图案，以暴露下层中形成的下层的蚀刻接触孔， 与图案对应，使得下面的第一布线组件暴露于外部，形成在下层上的固化的有机绝缘层和形成在有机绝缘层上的第二布线组件，使得第二布线组件是 通过蚀刻的接触孔连接到第一布线组件，以及相应的制造方法，包括形成第一布线组件 在第一布线组件上形成底层，形成有机绝缘层，使得有机绝缘层覆盖图案化有机绝缘层的下层，从而形成暴露下层，蚀刻的接触孔 所述下层通过所述接触孔暴露，使得所述下面的第一布线组件暴露于外部，固化所述有机绝缘层，以及在所述有机绝缘层上形成第二布线组合件，使得所述第二布线组件被连接 通过接触孔到第一布线组件。

公开(公告)号：US20070263134A1

公开(公告)日：2007-11-15

申请号：US11744457

申请日：2007-05-04

Applicant: Beom-Jun Kim ,  Jong-Hwan Lee ,  Sang-Jin Jeon ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

Inventor： Beom-Jun Kim ,  Jong-Hwan Lee ,  Sang-Jin Jeon ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

IPC: G02F1/1333

CPC classification number: G02F1/136213 ,  G02F1/136259 ,  G02F1/136286

Abstract: A liquid crystal display that is subject to pixel-high defects due to manufacturing anomalies is provided with programmable repair means for each pixel electrode. In one embodiment, a transistor-array substrate is provided with plural gate lines that are separated from each other by a first interval, plural data lines that are insulated from the gate lines while crossing the gate lines, and separated from each other by a second interval larger than the first interval, thereby defining plural pixel areas. Each pixel area has a corresponding pixel unit comprising a switching device, pixel electrode, and repair electrode. The repair electrode branches from a neighboring gate line and extends such that the repair electrode is in overlapping spaced-apart relation with the pixel electrode and selectively connectable to the pixel electrode. Accordingly, a pixel where a high pixel defect occurs can be repaired by selective connection with the repair electrode, thereby improving display quality of the liquid crystal display.

Abstract translation: 由于制造异常而受到像素高缺陷的液晶显示器，为每个像素电极提供可编程修复装置。 在一个实施例中，晶体管阵列基板设置有多条栅极线，它们彼此分开第一间隔，多条数据线在与栅极线交叉的同时与栅极线绝缘并且彼此分开第二个 间隔大于第一间隔，从而限定多个像素区域。 每个像素区域具有包括开关器件，像素电极和修复电极的对应像素单元。 修复电极从相邻的栅极线分支并延伸，使得修复电极与像素电极重叠间隔开，并且可选择性地连接到像素电极。 因此，可以通过与修复电极的选择性连接来修复发生高像素缺陷的像素，从而提高液晶显示器的显示质量。

公开(公告)号：US09164613B2

公开(公告)日：2015-10-20

申请号：US13299587

申请日：2011-11-18

Applicant: Sang-Jin Jeon ,  Ho-Kyoon Kwon

Inventor： Sang-Jin Jeon ,  Ho-Kyoon Kwon

IPC: G02F1/1335 ,  G02F1/1343 ,  G06F3/041 ,  G06F3/045 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1362 ,  H01L29/417

CPC classification number: G06F3/0412 ,  G02F1/13338 ,  G02F1/133707 ,  G02F1/13624 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2001/134381 ,  H01L29/41733

Abstract: A touch display substrate includes a first data line, a first gate line, a first pixel electrode, a second gate line, a second pixel electrode, a sensor data line and a first sensor electrode. The first data line extends along a first direction. The first gate line extends along a second direction. The first pixel electrode is electrically connected to the first data line and the first gate line. The second gate line is substantially parallel with the first gate line. The second pixel electrode is adjacent to the first pixel electrode and electrically connected to the first data line and the second gate line. The sensor data line is adjacent to the second pixel electrode and substantially parallel to the first data line. The first sensor electrode is electrically connected to the sensor data line.

Abstract translation: 触摸显示基板包括第一数据线，第一栅极线，第一像素电极，第二栅极线，第二像素电极，传感器数据线和第一传感器电极。 第一数据线沿着第一方向延伸。 第一栅极线沿第二方向延伸。 第一像素电极电连接到第一数据线和第一栅极线。 第二栅极线基本上与第一栅极线平行。 第二像素电极与第一像素电极相邻并且电连接到第一数据线和第二栅极线。 传感器数据线与第二像素电极相邻并且基本上平行于第一数据线。 第一传感器电极电连接到传感器数据线。

公开(公告)号：US09109055B2

公开(公告)日：2015-08-18

申请号：US14112849

申请日：2012-08-24

Applicant: Won-Hee Kim ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Sang-Jin Jeon

Inventor： Won-Hee Kim ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Sang-Jin Jeon

IPC: C08F4/64 ,  C08F4/76 ,  B01J23/00 ,  B01J21/06 ,  C08F10/00

CPC classification number: C08F4/76 ,  B01J21/06 ,  C08F4/64 ,  C08F4/659 ,  C08F10/00 ,  C08F4/64141 ,  C08F4/65908 ,  C08F210/16 ,  C08F210/14 ,  C08F2500/03

Abstract: The present invention relates to a transition metal catalyst composition which can exhibit high reactivity in a polymerization reaction of a polyolefin and can easily control characteristics such as chemical structure, molecular weight distribution, mechanical properties, and the like of a synthesized polyolefin, and a method of preparing a polyolefin using the catalyst composition.

Abstract translation: 本发明涉及能够在聚烯烃的聚合反应中表现出高反应性的过渡金属催化剂组合物，并且可以容易地控制合成聚烯烃的化学结构，分子量分布，机械性能等特性，以及方法 使用该催化剂组合物制备聚烯烃。

公开(公告)号：US09035006B2

公开(公告)日：2015-05-19

申请号：US13980869

申请日：2012-01-19

Applicant: Sang-Jin Jeon ,  Seung-Ki Park ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An

Inventor： Sang-Jin Jeon ,  Seung-Ki Park ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An

IPC: C08F210/16 ,  C08F295/00 ,  C08J5/18 ,  C08F297/08 ,  C08F301/00

CPC classification number: C08F295/00 ,  C08F210/16 ,  C08F297/08 ,  C08F301/00 ,  C08F2500/10 ,  C08J5/18 ,  C08J2323/16

Abstract: The present description relates to an olefin block copolymer preferably useful to form nonslip pads due to excellences in elasticity and heat resistance, and a sheet-shaped molded body comprising the olefin block copolymer The olefin block copolymer includes a plurality of blocks or segments, each of which includes an ethylene or propylene repeating unit and an α-olefin repeating unit at different weight fractions. The olefin block copolymer satisfies a defined relationship when a load of 5 to 10 kg is applied to a sheet-shaped molded body of the block copolymer for 12 hours or longer at a temperature of 60° C. or higher, and then removed.

Abstract translation: 本发明涉及由于弹性和耐热性优异而优选用于形成非滑垫的烯烃嵌段共聚物和包含烯烃嵌段共聚物的片状成型体。烯烃嵌段共聚物包括多个嵌段或链段 其包括乙烯或丙烯重复单元和不同重量分数的α-烯烃重复单元。 当在60℃以上的温度下对嵌段共聚物的片状成型体施加5〜10kg的负荷12小时以上时，烯烃嵌段共聚物满足规定的关系，然后除去。

公开(公告)号：US08759461B2

公开(公告)日：2014-06-24

申请号：US13386282

申请日：2010-07-23

Applicant: Sang-Jin Jeon ,  Hoon Chae ,  Cheon-Il Park ,  Kyung-Seop Noh ,  Won-Hee Kim

Inventor： Sang-Jin Jeon ,  Hoon Chae ,  Cheon-Il Park ,  Kyung-Seop Noh ,  Won-Hee Kim

IPC: C08F4/76 ,  C08F4/64 ,  C08F4/52

CPC classification number: C07D215/12

Abstract: The present invention relates to a novel post metallocene-type ligand compound, to a metal compound containing the ligand compound, to a catalytic composition containing the metal compound, and to a method for preparing same, as well as to a method for preparing olefin polymers using the catalytic composition. The present invention provides a catalyst for preparing special polyolefin-based polymers having excellent activity.

Abstract translation: 本发明涉及一种新颖的后茂金属型配体化合物，含有配体化合物的金属化合物，涉及含有金属化合物的催化组合物及其制备方法，以及制备烯烃聚合物的方法 使用催化剂组合物。 本发明提供一种制备具有优异活性的特种聚烯烃基聚合物的催化剂。

公开(公告)号：US08003988B2

公开(公告)日：2011-08-23

申请号：US12612448

申请日：2009-11-04

Applicant: Sang-Jin Jeon

Inventor： Sang-Jin Jeon

IPC: H01L29/04 ,  H01L29/10 ,  G02F1/1333 ,  H01L21/00

CPC classification number: G02F1/136204 ,  G02F1/136259 ,  G02F2001/133388 ,  G02F2001/134318 ,  G02F2001/136263 ,  G02F2001/136272 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2330/04 ,  G09G2330/08 ,  H01L27/124

Abstract: A thin film transistor array panel comprises a repair line disposed in a peripheral area of a display area and being configured to repair when at least one of a gate line and a data line are disconnected, and a detour line disposed in the peripheral area and comprising at least one resistor having higher resistance than a remaining portion of the detour line, wherein both ends of the detour line are connected to the repair line to protect the array panel.

Abstract translation: 薄膜晶体管阵列面板包括设置在显示区域的外围区域中的修复线，并且被配置为当栅极线和数据线中的至少一个断开时进行修复，以及设置在周边区域中的迂回线，并且包括 至少一个电阻器具有比绕行线路的剩余部分更高的电阻，其中绕线的两端连接到修复线以保护阵列面板。

公开(公告)号：US07880503B2

公开(公告)日：2011-02-01

申请号：US12503145

申请日：2009-07-15

Applicant: Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

Inventor： Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: G11C8/08 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184

Abstract: A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.

Abstract translation: 驱动栅极线的方法用于通过将栅极线的输出信号输出来激活栅极线。 基于进位信号或来自前一级的垂直起始信号来升高第一节点。 基于提升的第一时钟信号，通过当前级的输出端输出被上拉的门信号。 响应于来自下一级的输出信号或垂直起始信号，通过当前级的输出端输出截止电压。 第一节点响应于来自下一级的输出信号或来自最后一级的进位信号而放电。 通过向第一节点提供负纹波电压来消除第一节点处的正纹波电压。