公开(公告)号：US6091593A

公开(公告)日：2000-07-18

申请号：US956271

申请日：1997-10-22

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/02 ,  H02H3/22

CPC classification number: H01L27/0266 ,  H01L27/0251 ,  H01L27/0259

Abstract: A transient voltage pump is provided to generate a negative voltage pulse for triggering turn-on of an ESD protection device. As VDD-to-VSS voltage increases rapidly in the initial ESD event, the voltage across the ESD protection device is larger than the trigger voltage of the ESD device while the ESD voltage is still at substantially lower voltage. These negative voltage pulses are used to earlier trigger the NMOS transistor before the ESD transient voltage actually reaches the trigger voltage. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.

Abstract translation: 提供瞬态电压泵以产生用于触发ESD保护装置的导通的负电压脉冲。 由于VDD-VSS电压在初始ESD事件中迅速增加，因此ESD保护器件上的电压大于ESD器件的触发电压，而ESD电压仍处于基本较低的电压。 在ESD瞬变电压实际达到触发电压之前，这些负电压脉冲用于较早触发NMOS晶体管。 本发明改进了ESD保护装置（例如MOSFET或双极晶体管）的ESD性能，其被提供用于在ESD事件期间保护电源总线或IC引脚。

公开(公告)号：US06043967A

公开(公告)日：2000-03-28

申请号：US956270

申请日：1997-10-22

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H02H9/04 ,  H02H3/22

CPC classification number: H02H9/046

Abstract: A transient voltage pump is provided to generate a high voltage pulse for triggering turn-on of an ESD protection device. As VDD-to-VSS voltage increases rapidly in the initial ESD event, the voltages of the high voltage pulses are larger than the trigger voltage of the ESD device while the ESD voltage is still at substantially lower voltage. These high voltage pulses are used to early trigger the NMOS transistor before the ESD transient voltage actually reaches the trigger voltage. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.

Abstract translation: 提供瞬态电压泵以产生用于触发ESD保护装置的导通的高电压脉冲。 由于VDD-VSS电压在初始ESD事件中迅速增加，所以高电压脉冲的电压大于ESD器件的触发电压，而ESD电压仍处于基本较低的电压。 这些高电压脉冲用于在ESD瞬态电压实际达到触发电压之前提早触发NMOS晶体管。 本发明改进了ESD保护装置（例如MOSFET或双极晶体管）的ESD性能，其被提供用于在ESD事件期间保护电源总线或IC引脚。

公开(公告)号：US5870268A

公开(公告)日：1999-02-09

申请号：US954945

申请日：1997-10-22

Applicant: Shi-Tron Lin ,  Du-Zen Peng ,  Shyh-Chyi Wong

Inventor： Shi-Tron Lin ,  Du-Zen Peng ,  Shyh-Chyi Wong

IPC: H01L27/02 ,  H02H3/22

CPC classification number: H01L27/0251 ,  H01L27/0259 ,  H01L27/0266

Abstract: A transient switching circuit is provided to generate a voltage signal with fast voltage switching phenomenon during the initial ESD transient. The voltage signal is applied to a current spike generator for generating a current spike which forward bias an n+/pwell diode for injecting minority carriers into a substrate on which ESD protection device is embodied. The injected minority carriers are used to trigger turn-on of the ESD protection device. These minority carriers flow toward the drain-substrate junction of the NMOS transistor such that the NMOS transistor is triggered at a trigger voltage lower than that provided by the prior arts. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.

Abstract translation: 提供瞬态开关电路以在初始ESD瞬变期间产生具有快速电压切换现象的电压信号。 电压信号被施加到电流尖峰发生器，用于产生正向偏置n + / pwell二极管的电流尖峰，用于将少数载流子注入到其上体现ESD保护装置的衬底中。 注入的少数载流子用于触发ESD保护装置的导通。 这些少数载流子流向NMOS晶体管的漏极 - 衬底结，使得在比现有技术提供的触发电压低的触发电压下触发NMOS晶体管。 本发明改进了ESD保护装置（例如MOSFET或双极晶体管）的ESD性能，其被提供用于在ESD事件期间保护电源总线或IC引脚。

公开(公告)号：US5869870A

公开(公告)日：1999-02-09

申请号：US677109

申请日：1996-07-09

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L23/50 ,  H01L23/60 ,  H01L23/48

CPC classification number: H01L23/50 ,  H01L23/60 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/13034 ,  H01L2924/13091 ,  H01L2924/14

Abstract: An ESD protective device for protection of an integrated circuit (IC) package from electrostatic discharge damage. The ESD protective device protects the internal circuit of the IC connected to wired pins of the IC package against ESD damage due to ESD stress in neighboring no-connect pins. The ESD protective device includes an ESD protective unit coupled to the power bus and a bonding pad coupled between this ESD protective device and the no-connect pin. The ESD protective unit causes ESD stress applied to the no-connect pin to be diverted to the power bus, thus preventing ESD transfer between a no-connect pin and an active pin, which could damage the internal circuit.

公开(公告)号：US5818086A

公开(公告)日：1998-10-06

申请号：US661659

申请日：1996-06-11

Applicant: Shi-Tron Lin ,  Alex C. Wang ,  Hsin-Chang Lin

Inventor： Shi-Tron Lin ,  Alex C. Wang ,  Hsin-Chang Lin

IPC: H01L27/02 ,  H01L29/74 ,  H01L23/62 ,  H01L29/00 ,  H01L31/111

CPC classification number: H01L27/0248 ,  H01L2924/0002

Abstract: In accordance with the invention, an integrated circuit has a first ESD protection circuit for each input pin which is not adjacent a non-wired IC pin and a second ESD protection circuit for each input pin which is adjacent a non-wired pin. The second ESD protection circuit has a greater ESD protection capability than the first ESD protection circuit. The second ESD protection circuit has a capability of protecting an input pin when an ESD stress occurs at an adjacent non-wired pin. The second ESD protection circuit includes, for example, additional ESD protection elements in comparison to the first ESD protection circuit. Alternatively, the second ESD protection circuit has one ESD protection element which is larger in size or is otherwise different than a corresponding ESD protection element in the first ESD protection circuit. The invention has the advantage of not changing the definition of the non-wired IC pins and also does not cost large amounts of chip real estate because the ESD protection circuit is reinforced for only those input pins which are adjacent non-wired pins. The ESD protection circuit is not reinforced for I/O pins, VDD pins, VSS pins, and input pins which are not adjacent non-wired pins.

Abstract translation: 根据本发明，集成电路具有用于每个输入引脚的不与非有线IC引脚相邻的第一ESD保护电路和用于与非有线引脚相邻的每个输入引脚的第二ESD保护电路。 第二ESD保护电路具有比第一ESD保护电路更大的ESD保护能力。 第二ESD保护电路具有在相邻的非接线引脚处产生ESD应力时保护输入引脚的能力。 与第一ESD保护电路相比，第二ESD保护电路包括例如额外的ESD保护元件。 或者，第二ESD保护电路具有一个ESD保护元件，该ESD保护元件的尺寸较大或者与第一ESD保护电路中相应的ESD保护元件不同。 本发明的优点在于，不改变非有线IC引脚的定义，并且由于ESD保护电路只对那些相邻非有线引脚的输入引脚加强，所以不会花费大量的芯片空间。 对于I / O引脚，VDD引脚，VSS引脚和非相邻引脚的输入引脚，ESD保护电路不加强。

公开(公告)号：US5763919A

公开(公告)日：1998-06-09

申请号：US677034

申请日：1996-07-08

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0266

Abstract: A MOS transistor array structure for an electro-static discharge protection circuit in a semiconductor integrated circuit device, having dispersed parallel discharge paths. The MOS transistor array includes an n-well formed in a silicon substrate of the fabricated semiconductor device. A first dispersed drain region is formed in the n-well, and a source region is formed in the silicon substrate. A second dispersed drain region is formed in both the silicon substrate and the n-well. A gate of the transistor array is formed on the silicon substrate, and a first field oxide region is distributed at least partially in the dispersed drain region, so as to improve the even distribution of electric current in the event of an electro-static discharge. The transistor structure is compatible with a silicided process of device fabrication for fast device operation. Fabrication of the structure does not require additional procedural steps for achieving this compatibility.

Abstract translation: 一种用于半导体集成电路器件中的静电放电保护电路的MOS晶体管阵列结构，具有分散的平行放电路径。 MOS晶体管阵列包括在制造的半导体器件的硅衬底中形成的n阱。 在n阱中形成第一分散的漏极区，并且在硅衬底中形成源极区。 在硅衬底和n阱中形成第二分散漏极区。 晶体管阵列的栅极形成在硅衬底上，并且第一场氧化物区域至少部分地分布在分散的漏极区域中，以便在静电放电的情况下改善电流的均匀分布。 晶体管结构与用于快速器件操作的器件制造的硅化工艺兼容。 结构的制作不需要额外的程序步骤来实现这种兼容性。

公开(公告)号：US5721439A

公开(公告)日：1998-02-24

申请号：US630127

申请日：1996-04-10

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L27/0251

Abstract: A MOS transistor structure for an electro-static discharge (ESD) protection circuit of an integrated circuit device. The ESD protection transistor has a structure that comprises a drain diffusion region formed in the silicon substrate of the integrated circuit device, a source diffusion region formed in the silicon substrate, a gate formed in the silicon substrate, and a number of isolated islands evenly distributed throughout the drain diffusion region. The isolated islands provide substantially uniform diffusion resistance between the drain contacts and the gate while increasing the diffusion resistance of the drain region to a level suitable for ESD current protection. The disclosed MOS transistor structure may be fabricated by a salicide technology-based fabrication procedure that is completely compatible with the salicide technology used for the making of the circuitry for the IC device.

Abstract translation: 一种用于集成电路器件的静电放电（ESD）保护电路的MOS晶体管结构。 ESD保护晶体管具有包括形成在集成电路器件的硅衬底中的漏极扩散区域，形成在硅衬底中的源极扩散区域，形成在硅衬底中的栅极和多个均匀分布的隔离岛的结构 遍及漏极扩散区域。 隔离岛在漏极接触和栅极之间提供基本均匀的扩散电阻，同时将漏极区域的扩散电阻提高到适合于ESD电流保护的水平。 所公开的MOS晶体管结构可以通过基于自对准硅化物技术的制造程序来制造，其完全兼容用于制造用于IC器件的电路的自对准硅化物技术。

公开(公告)号：US4155553A

公开(公告)日：1979-05-22

申请号：US710919

申请日：1976-08-02

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: A63B47/00 ,  A63B63/04 ,  A63B65/12

CPC classification number: A63B65/12 ,  A63B47/00

Abstract: A ball game machine, which after being hit by an incoming ball, will return another ball with a minimum loss of energy. The incoming ball stops at the ball receiver and transmits almost all of its kinetic energy to the machine through proper inertia design. Instantaneously, the recoiling ball receiver mechanically causes a bat to strike a second ball which has been stored in a collector. The incoming ball then drops into the collector and becomes a stored ball so that the operation can be repeated.

Abstract translation: 一个球形游戏机在被一个进球击中后，会以最小的能量损失返回另一个球。 进球在球接收器处停止，并通过适当的惯性设计将几乎所有的动能传递到机器。 瞬间，反弹球接收器机械地使蝙蝠撞击已经存储在收集器中的第二球。 然后，进入的球落入收集器中并变成储存的球，使得可以重复该操作。

公开(公告)号：US07075154B2

公开(公告)日：2006-07-11

申请号：US10395328

申请日：2003-03-24

Applicant: Shi-Tron Lin ,  Wei-Fan Chen

Inventor： Shi-Tron Lin ,  Wei-Fan Chen

IPC: H01L23/62

CPC classification number: H01L27/027 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge protection device formed on a substrate. The electrostatic discharge protection device includes a first isolation region formed over the substrate, an active region formed over the substrate and enclosed by the first isolation region, a second isolation region formed on the substrate and substantially surrounded by the active region, a first gate element formed in the active region, the first gate element having a first end extending over the first isolation region and a second end extending over the second isolation region, a drain region formed in the active region at a first side of the first gate element, a source region formed in the active region at a second side of the first gate element, a drain contact for electrically coupling the drain region to a first node, and a source contact for electrically coupling the source region to a second node.

公开(公告)号：US06852568B2

公开(公告)日：2005-02-08

申请号：US10281069

申请日：2002-09-16

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L23/60 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/60 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

Abstract translation: 提供了一种引脚分配方法，用于在IC封装上使用以布置引脚连接。 引脚分配方法可以改善IC封装中封装的IC芯片的静电放电（ESD）保护能力。 具体地，引脚分配方法将IC封装的无连接引脚组合成组，然后分配将要连接到IC芯片的电源总线的每个不连接引脚组的两个引脚中的每一个引脚。 这样可以提高无连接引脚的ESD保护能力。 此外，引脚分配方法可以简化IC封装的布线复杂性。