公开(公告)号：US20090283814A1

公开(公告)日：2009-11-19

申请号：US12122739

申请日：2008-05-19

申请人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Chrong-Jung Lin

发明人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Chrong-Jung Lin

IPC分类号： H01L27/112

CPC分类号： H01L27/112 ,  G11C17/16 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A non-volatile memory cell includes an ion well of a semiconductor substrate; a first half-transistor having a firs select gate, a first diffusion region in the ion well, and a first gate dielectric layer between the first select gate and the ion well; a second half-transistor disposed adjacent to the first half-transistor, wherein the second half-transistor has a second select gate spaced apart from the first select gate, a second diffusion region in the ion well, and a second gate dielectric layer between the second select gate and the ion well. The first and second half-transistors are mirror-symmetrical to each other.

摘要翻译： 非易失性存储单元包括半导体衬底的离子阱; 具有第一选择栅极的第一半晶体管，离子阱中的第一扩散区域和第一选择栅极与离子阱之间的第一栅极介电层; 与所述第一半晶体管相邻设置的第二半晶体管，其中所述第二半晶体管具有与所述第一选择栅极间隔开的第二选择栅极，所述离子阱中的第二扩散区域和所述第二栅极介电层之间的第二栅极介电层 第二选择门和离子阱。 第一和第二半晶体管彼此镜像对称。

公开(公告)号：US20090244985A1

公开(公告)日：2009-10-01

申请号：US12056288

申请日：2008-03-27

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Sheng-Yu Wang ,  Cheng-Yen Shen

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Sheng-Yu Wang ,  Cheng-Yen Shen

IPC分类号： G11C16/16

CPC分类号： G11C16/0466 ,  G11C16/14

摘要： A present invention relates to a method of erasing a P-channel non-volatile memory is provided. This P-channel non-volatile memory includes a select transistor and a memory cell connected in series and disposed on a substrate. In the method of erasing the P-channel non-volatile memory, holes are injected into a charge storage structure by substrate hole injection effect. Hence, the applied operational voltage is low, so the power consumption is lowered, and the efficiency of erasing is enhanced. As a result, an operational speed of the memory is accelerated, and the reliability of the memory is improved.

摘要翻译： 本发明涉及一种擦除P信道非易失性存储器的方法。 该P沟道非易失性存储器包括选择晶体管和串联连接并设置在基板上的存储单元。 在擦除P沟道非易失性存储器的方法中，通过衬底空穴注入效应将空穴注入电荷存储结构。 因此，施加的工作电压低，因此功耗降低，并且提高了擦除效率。 结果，加速了存储器的操作速度，并提高了存储器的可靠性。

公开(公告)号：US07447082B2

公开(公告)日：2008-11-04

申请号：US11555676

申请日：2006-11-01

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

摘要翻译： 提供了与纳米级半导体制造工艺完全兼容的单一多晶非易失性存储单元。 单多晶非易失性存储单元包括离子阱，形成在离子阱上的栅极，栅极和离子阱之间的栅极电介质层，栅极侧壁上的电介质叠层，源极掺杂区和 漏极掺杂区域。 电介质堆叠层包括沉积在栅极的侧壁上并延伸到离子阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。 氮化硅层用作电荷捕获层。

公开(公告)号：US07433243B2

公开(公告)日：2008-10-07

申请号：US11557975

申请日：2006-11-09

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

摘要翻译： 提供了形成在第一导电型基板上的非易失性存储器。 非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。 栅极形成在第一导电类型的基板上。 第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。 电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。 第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。 第二面与第一面相反。

公开(公告)号：US20070109861A1

公开(公告)日：2007-05-17

申请号：US11555676

申请日：2006-11-01

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

摘要翻译： 提供了与纳米级半导体制造工艺完全兼容的单一多晶非易失性存储单元。 单多晶非易失性存储单元包括离子阱，形成在离子阱上的栅极，栅极和离子阱之间的栅极电介质层，栅极侧壁上的电介质叠层，源极掺杂区和 漏极掺杂区域。 电介质堆叠层包括沉积在栅极的侧壁上并延伸到离子阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。 氮化硅层用作电荷捕获层。

公开(公告)号：US20060018161A1

公开(公告)日：2006-01-26

申请号：US10905736

申请日：2005-01-19

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Hong-Ping Tsai

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Hong-Ping Tsai

IPC分类号： G11C16/04

CPC分类号： G11C16/0441 ,  H01L27/115

摘要： An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a first floating gate channel region formed between its drain and source, and a common floating gate overlying the floating gate channel region; a second select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; and a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a second floating gate channel region formed between its drain and source, and the common floating gate overlying the second floating gate channel region.

摘要翻译： 可擦除可编程非易失性存储单元包含离子阱; 包括选择栅极的第一选择晶体管，形成在所述离子阱中的源极/漏极以及在其源极和漏极之间形成的沟道区域; 具有漏极的第一浮栅晶体管，耦合到所述第一选择晶体管的漏极的源极，形成在其漏源和源极之间的第一浮置栅极沟道区和覆盖所述浮置栅极沟道区的公共浮动栅; 包括选择栅极的第二选择晶体管，形成在离子阱中的源极/漏极，以及在其源极和漏极之间形成的沟道区域; 以及第二浮栅晶体管，其具有漏极，耦合到所述第二选择晶体管的漏极的源极，形成在其漏极和源极之间的第二浮置栅极沟道区域以及覆盖所述第二浮置栅极沟道区域的所述公共浮动栅极。

公开(公告)号：USH1716H

公开(公告)日：1998-04-07

申请号：US843487

申请日：1997-04-16

申请人： Larry Alan Rapp ,  Shih-Chen Wang

发明人： Larry Alan Rapp ,  Shih-Chen Wang

IPC分类号： C10L1/06 ,  C10L1/04

CPC分类号： C10L1/06

摘要： A method is provided for manufacturing a chemical mixture, such as a gasoline blend, which conforms to a set of regulations set by an outside public agency. The invention is directed to a set of regulations which require the manufacturer to prepare a master specification which sets control limits on the chemical characteristics of the chemical mixture and require that the master specification conform to a set of controlling criteria which are dependent upon such control limits--such as predicted exhaust pollution emissions from the burning of the subject gasoline blend. The method comprises the steps of: (a) blending quantities of chemical components to create a chemical mixture conforming to the controlling criteria, (b) analyzing the chemical mixture to determine the chemical characteristics of the chemical mixture, (c) preparing a test specification which conforms to the chemical characteristics of the chemical mixture, (d) determining whether the test specification conforms to the controlling criteria, and (e) accepting the test specification as the master specification if the determination in step (d) is positive.

摘要翻译： 提供了一种用于制造化学混合物（例如汽油混合物）的方法，其符合由外部公共机构设定的一套规定。 本发明涉及一组规定，要求制造商制备主要规范，其规定对化学混合物的化学特性的控制限制，并要求主规范符合依赖于这种控制限制的一组控制标准 如预测主题汽油混合燃烧所产生的尾气污染排放。 该方法包括以下步骤：（a）混合数量的化学成分以产生符合控制标准的化学混合物，（b）分析化学混合物以确定化学混合物的化学特性，（c）制备测试规范 符合化学混合物的化学特性，（d）确定测试规范是否符合控制标准，以及（e）如果步骤（d）中的测定为阳性，则将测试规范作为主要规范。