公开(公告)号：US07447082B2

公开(公告)日：2008-11-04

申请号：US11555676

申请日：2006-11-01

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

摘要翻译： 提供了与纳米级半导体制造工艺完全兼容的单一多晶非易失性存储单元。 单多晶非易失性存储单元包括离子阱，形成在离子阱上的栅极，栅极和离子阱之间的栅极电介质层，栅极侧壁上的电介质叠层，源极掺杂区和 漏极掺杂区域。 电介质堆叠层包括沉积在栅极的侧壁上并延伸到离子阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。 氮化硅层用作电荷捕获层。

公开(公告)号：US07433243B2

公开(公告)日：2008-10-07

申请号：US11557975

申请日：2006-11-09

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

摘要翻译： 提供了形成在第一导电型基板上的非易失性存储器。 非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。 栅极形成在第一导电类型的基板上。 第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。 电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。 第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。 第二面与第一面相反。

公开(公告)号：US20070109861A1

公开(公告)日：2007-05-17

申请号：US11555676

申请日：2006-11-01

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

摘要翻译： 提供了与纳米级半导体制造工艺完全兼容的单一多晶非易失性存储单元。 单多晶非易失性存储单元包括离子阱，形成在离子阱上的栅极，栅极和离子阱之间的栅极电介质层，栅极侧壁上的电介质叠层，源极掺杂区和 漏极掺杂区域。 电介质堆叠层包括沉积在栅极的侧壁上并延伸到离子阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。 氮化硅层用作电荷捕获层。

公开(公告)号：US20070111357A1

公开(公告)日：2007-05-17

申请号：US11557111

申请日：2006-11-07

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L21/00

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

摘要翻译： 提供了形成在第一导电型基板上的非易失性存储器。 非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。 栅极形成在第一导电类型的基板上。 第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。 电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。 第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。 第二面与第一面相反。

公开(公告)号：US20080138956A1

公开(公告)日：2008-06-12

申请号：US11962126

申请日：2007-12-21

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L21/336

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.

摘要翻译： 提供了形成在第一导电类型基板上的半导体器件。 该器件包括栅极，第二导电型漏极区域，第二导电型源极区域和第二导电型第一轻掺杂区域。 栅极形成在第一导电类型的基板上。 第二导电型漏极区域和第二导电型源极区域形成在栅极两侧的第一导电型衬底中。 第二导电类型的第一轻掺杂区域形成在栅极和第二导电型源极区域之间的第一导电型衬底中。

公开(公告)号：US20070109869A1

公开(公告)日：2007-05-17

申请号：US11557975

申请日：2006-11-09

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

摘要翻译： 提供了形成在第一导电型基板上的非易失性存储器。 非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。 栅极形成在第一导电类型的基板上。 第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。 电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。 第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。 第二面与第一面相反。

公开(公告)号：US20070108470A1

公开(公告)日：2007-05-17

申请号：US11557112

申请日：2006-11-07

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L31/00

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.

摘要翻译： 提供了形成在第一导电类型基板上的半导体器件。 该器件包括栅极，第二导电型漏极区域，第二导电型源极区域和第二导电型第一轻掺杂区域。 栅极形成在第一导电类型的基板上。 第二导电型漏极区域和第二导电型源极区域形成在栅极两侧的第一导电型衬底中。 第二导电类型的第一轻掺杂区域形成在栅极和第二导电型源极区域之间的第一导电型衬底中。

公开(公告)号：US20070108507A1

公开(公告)日：2007-05-17

申请号：US11557974

申请日：2006-11-09

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L29/788

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

摘要翻译： 提供了形成在第一导电型基板上的非易失性存储器。 非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。 栅极形成在第一导电类型的基板上。 第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。 电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。 第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。 第二面与第一面相反。

公开(公告)号：US08089798B2

公开(公告)日：2012-01-03

申请号：US12627244

申请日：2009-11-30

申请人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

发明人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

IPC分类号： G11C17/00

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206

摘要： A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

摘要翻译： 提供了一种用于操作一次性可编程只读存储器（OTP-ROM）的方法。 OTP-ROM包括分别设置在衬底上的第一掺杂区域和第二掺杂区域之间的栅极电介质层上的第一栅极和第二栅极，其中第一栅极与第一掺杂区域相邻并耦合到第一掺杂区域 所述第二栅极与所述第二掺杂区相邻，所述第一栅极电耦合接地，并且通过击穿效应对所述OTP-ROM进行编程。 该方法包括在第二掺杂区域的电压高于第一掺杂区域的电压的条件下对OTP-ROM进行编程的步骤，第二栅极的电压高于阈值电压以通过 第二掺杂区域和第一掺杂区域和衬底处于参考电压。

公开(公告)号：US20100073985A1

公开(公告)日：2010-03-25

申请号：US12627244

申请日：2009-11-30

申请人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

发明人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

IPC分类号： G11C17/08

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206

摘要： A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

摘要翻译： 提供了一种用于操作一次性可编程只读存储器（OTP-ROM）的方法。 OTP-ROM包括分别设置在衬底上的第一掺杂区域和第二掺杂区域之间的栅极电介质层上的第一栅极和第二栅极，其中第一栅极与第一掺杂区域相邻并耦合到第一掺杂区域 所述第二栅极与所述第二掺杂区相邻，所述第一栅极电耦合接地，并且通过击穿效应对所述OTP-ROM进行编程。 该方法包括在第二掺杂区域的电压高于第一掺杂区域的电压的条件下对OTP-ROM进行编程的步骤，第二栅极的电压高于阈值电压以通过 第二掺杂区域和第一掺杂区域和衬底处于参考电压。