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    Cmos-compatible read only memory and method for fabricating the same
    9.
    发明授权
    Cmos-compatible read only memory and method for fabricating the same 有权
    Cmos兼容的只读存储器及其制造方法

    公开(公告)号：US06822286B2

    公开(公告)日：2004-11-23

    申请号：US10249370

    申请日：2003-04-03

    申请人： Ching-Hsiang Hsu ,  Wei-Zhe Wong ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Shih-Chan Huang ,  Ming-Chou Ho

    发明人： Ching-Hsiang Hsu ,  Wei-Zhe Wong ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Shih-Chan Huang ,  Ming-Chou Ho

    IPC分类号： H01L29788

    CPC分类号： H01L27/1126 ,  H01L27/112

    摘要： A CMOS-compatible read only memory (ROM) includes a first single-poly PMOS transistor that is serially electrically connected to a second single-poly PMOS transistor for recording digital data “1” or digital data “0”. The first and second single-poly PMOS transistors are both formed on an N-well of a P-type substrate. The first single-poly PMOS transistor includes a select gate electrically connected to a word line, a first P+ source doping region electrically connected to a source line, and a first P+ drain doping region. The second single-poly PMOS transistor includes a floating gate, a second P+ source doping region electrically connected to the first P+ drain doping region, and a second P+ drain doping region electrically connected to a bit line. The second P+ source doping region and the second P+ drain doping region define a floating gate channel region under the floating gate. A fast FPLD-to-ROM conversion method is also disclosed. After the final software code is fixed and the addresses where the memory units to be coded are determined, the FPLD are transformed into a ROM by either changing the layout of a photo mask that is used to define polysilicon gates to cancel the pre-selected floating gates according to the fixed software code, or by ion implanting the pre-selected floating gate channel regions underneath those floating gates where the memory units are to be coded.

    摘要翻译： CMOS兼容只读存储器（ROM）包括串联电连接到用于记录数字数据“1”或数字数据“0”的第二单多晶硅PMOS晶体管的第一单多晶硅PMOS晶体管。 第一和第二单多晶硅PMOS晶体管都形成在P型衬底的N阱上。 第一单多晶硅PMOS晶体管包括电连接到字线的选择栅极，电连接到源极线的第一P +源极掺杂区域和第一P +漏极掺杂区域。 第二单多晶硅PMOS晶体管包括浮置栅极，电连接到第一P +漏极掺杂区域的第二P +源极掺杂区域和电连接到位线的第二P +漏极掺杂区域。 第二P +源极掺杂区域和第二P +漏极掺杂区域在浮动栅极下方形成浮置栅极沟道区域。 还公开了一种快速的FPLD到ROM转换方法。 在固定最终软件代码并确定要编码的存储器单元的地址之后，通过改变用于定义多晶硅栅极的光掩模的布局来将FPLD转换成ROM，以取消预先选择的浮动 根据固定软件代码的门，或者通过离子注入要在存储器单元进行编码的那些浮动栅极之下的预先选择的浮置栅极沟道区域。

    SILICON-ON-INSULATOR (SOI) MEMORY DEVICE
    10.
    发明申请
    SILICON-ON-INSULATOR (SOI) MEMORY DEVICE 审中-公开
    绝缘体绝缘体（SOI）存储器件

    公开(公告)号：US20070296034A1

    公开(公告)日：2007-12-27

    申请号：US11759949

    申请日：2007-06-08

    申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

    发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558

    摘要： A single-poly SOI memory cell includes a PMOS select transistor serially connected with a floating-gate PMOS transistor on an SOI substrate. The PMOS select transistor includes a select gate, a P+ source region and a P+ drain/source region. The floating-gate PMOS transistor includes a floating gate, a P+ drain region and the P+ drain/source region, wherein the P+ drain/source region is shared by the PMOS select transistor and the floating-gate PMOS transistor. A floating first N+ doping region is disposed within the P+ drain/source region. The first N+ doping region, which is adjacent to the floating gate, acts as a source-tie pick-up.

    摘要翻译： 单多晶硅存储单元包括与SOI衬底上的浮栅PMOS晶体管串联连接的PMOS选择晶体管。 PMOS选择晶体管包括选择栅极，P + SUP源极区和P + SUP漏极/源极区。 浮置栅极PMOS晶体管包括浮置栅极，漏极和漏极区域，其中P + 漏极/源极区域由PMOS选择晶体管和浮置栅极PMOS晶体管共享。 漂浮的第一N + +掺杂区域设置在漏极/源极区域内。 与浮动栅极相邻的第一N + H + +掺杂区充当源极接头。