公开(公告)号：US20240134538A1

公开(公告)日：2024-04-25

申请号：US18330349

申请日：2023-06-05

Applicant: SILICON MOTION INC.

Inventor： Po-Sheng CHOU ,  Hsiang-Yu HUANG ,  Yan-Wen WANG

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.

公开(公告)号：US11966604B2

公开(公告)日：2024-04-23

申请号：US17879182

申请日：2022-08-02

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0604 ,  G06F3/0689

Abstract: The invention relates to a method and an apparatus for programming data into flash memory. The method includes: obtaining, by the accelerator, an execution table indicating that data related to the first virtual carrier need to go through a mid-end and a back-end processing stages earlier than data related to other virtual carriers; driving, by the routing engine, a host interface (I/F) to obtain data associated with all cargos in the second virtual carrier, updating the second cargo flags with third cargo flags to indicate that data associated with all the cargos in the second virtual carrier are prepared in the front-end processing stage; and determining, by the accelerator, that data associated with any cargo in the first virtual carrier hasn't been prepared according to information of the first cargo flags, and disallowing the second virtual carrier to proceed to the following processing stages.

公开(公告)号：US20240126473A1

公开(公告)日：2024-04-18

申请号：US18220288

申请日：2023-07-11

Applicant: Silicon Motion, Inc.

Inventor： Po-Lin Wu

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0614 ,  G06F3/064 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller performs a write operation in response to a write command issued by the host device, and during the write operation, the memory controller maintains a first quantity count value for counting a number of the predetermined memory block(s) that has/have been written with data, determines a number of the predetermined memory block(s) which is/are released in response to the write operation and maintains a second quantity count value based on this number. After the write operation, the memory controller updates the first quantity count value based on the second quantity count value when determining that the host device has requested to perform a flush operation on the predetermined memory blocks.

公开(公告)号：US20240118832A1

公开(公告)日：2024-04-11

申请号：US18230364

申请日：2023-08-04

Applicant: Silicon Motion, Inc.

Inventor： Yu-Hsien YAO

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0679

Abstract: The invention introduces a method for scheduling and executing host data-update commands. A first queue and a second queue are provided. The first queue includes first host data-update commands each including a first logical address. The second queue includes second host data-update commands each including a second logical address. A third host data-update command including a third logical address is generated and is labeled as a first type of host data-update command according to a host command received from a host side. All the first host data-update commands of the first queue are popped out and executed in response that the third logical address is the same as any first logical address. All the second host data-update commands of the second queue are popped out and executed in response that the third logical address is the same as any second logical address.

公开(公告)号：US20240111451A1

公开(公告)日：2024-04-04

申请号：US17959308

申请日：2022-10-04

Applicant: Silicon Motion, Inc.

Inventor： Yu-Chih Lin

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0607 ,  G06F3/0679

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

公开(公告)号：US20240103732A1

公开(公告)日：2024-03-28

申请号：US18142590

申请日：2023-05-03

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0646 ,  G06F3/0653 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. The memory controller maintains a write count for each sub-region of the memory device. When the memory controller has selected one or more sub-regions to perform a data rearrangement procedure, the memory controller further determines whether a selected sub-region is a hot-write sub-region according to the write count corresponding to the selected sub-region. When the memory controller determines that the selected sub-region is not a hot-write sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses. When the memory controller determines that the selected sub-region is a hot-write sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

公开(公告)号：US11933847B2

公开(公告)日：2024-03-19

申请号：US17737351

申请日：2022-05-05

Applicant: Silicon Motion, Inc.

Inventor： Han-Chih Tsai ,  Ming-Kun Chung

IPC: G06F11/00 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/10 ,  G06F11/263 ,  G06F11/273 ,  G06F13/38

CPC classification number: G01R31/318597 ,  G01R31/318307 ,  G01R31/318572 ,  G06F11/1004 ,  G06F11/263 ,  G06F11/273 ,  G06F13/382

Abstract: The invention relates to an apparatus and a system for debugging a solid-state disk (SSD) device. The apparatus includes a Joint Test Action Group (JTAG) add-on board; and a Raspberry Pi. The Raspberry Pi includes a General-Purpose Input/Output (GPIO) interface (I/F), coupled to the JTAG add-on board; and a processing unit, coupled to the GPIO I/F. The processing unit is arranged operably to: simulate to issue a plurality of JTAG command through the GPIO I/F to the SSD device for dumping data generated by the SSD device during operation from the SSD device.

公开(公告)号：US11914901B2

公开(公告)日：2024-02-27

申请号：US17852403

申请日：2022-06-29

Applicant: Silicon Motion, Inc.

Inventor： Tsu-Han Lu ,  Hsiao-Chang Yen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

Abstract: A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface includes: using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal.

公开(公告)号：US11901961B2

公开(公告)日：2024-02-13

申请号：US17951090

申请日：2022-09-22

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen Shih

IPC: H04B17/11 ,  H04J3/04 ,  H04B17/21

CPC classification number: H04B17/11 ,  H04B17/21 ,  H04J3/04

Abstract: A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

公开(公告)号：US20240045798A1

公开(公告)日：2024-02-08

申请号：US18380568

申请日：2023-10-16

Applicant: SILICON MOTION INC.

Inventor： Chao-Kuei Hsieh

IPC: G06F12/02 ,  G11C7/20 ,  G06F3/06 ,  G06F3/08 ,  G11C7/10 ,  G11C16/16 ,  G11C16/26

CPC classification number: G06F12/0246 ,  G11C7/20 ,  G06F3/0679 ,  G06F3/08 ,  G11C7/1063 ,  G11C7/109 ,  G11C16/16 ,  G11C16/26

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.