Memory controller, test device and link identification method

    公开(公告)号:US11755439B2

    公开(公告)日:2023-09-12

    申请号:US17700514

    申请日:2022-03-22

    摘要: A memory controller coupled to a memory device and configured to control access operations of the memory device includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and configured to set a value of a predetermined parameter to a specific value after the memory controller powers up and start to perform a link flow to try to establish a transmission link via the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface and the predetermined parameter is related to reception of the host interface. After the link flow is completed, the microprocessor is further configured to identify an object device with which the host interface establishes the transmission link according to the specific value and at least one of a plurality of attribute parameters associated with the transmission link.

    Data storage device and non-volatile memory control method

    公开(公告)号:US11748023B2

    公开(公告)日:2023-09-05

    申请号:US17025004

    申请日:2020-09-18

    发明人: Yu-Hsiang Chung

    IPC分类号: G06F3/06

    摘要: Power recovery for data storage devices with an efficient space trimming technology is shown. A controller scans a non-volatile memory according to a programming order, collects a sequence of trimming information flags, and interprets a sequence of storage information scanned from the non-volatile memory to identify logical addresses and trimming code. Based on the logical addresses, a host-to-device mapping (H2F) table is rebuilt. Based on the trimming code, information of medium-length trimming and information of long-length trimming are recognized from a storage area of the non-volatile memory. According to the trimming information for medium-length trimming, dummy mapping data is programmed to the H2F table. According to the trimming information for long-length trimming, a trimming bitmap (TBM) is rebuilt. Each bit in the TBM marks space trimming of a first length.

    Initialization methods and associated controller, memory device and host

    公开(公告)号:US11726686B2

    公开(公告)日:2023-08-15

    申请号:US17843691

    申请日:2022-06-17

    发明人: Chao-Kuei Hsieh

    IPC分类号: G06F3/06 G06F13/42

    摘要: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

    Fractional frequency divider and flash memory controller

    公开(公告)号:US11705907B2

    公开(公告)日:2023-07-18

    申请号:US17707992

    申请日:2022-03-30

    摘要: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

    APPARATUS AND METHOD FOR DETECTING ERRORS DURING DATA ENCRYPTION

    公开(公告)号:US20230198754A1

    公开(公告)日:2023-06-22

    申请号:US18076615

    申请日:2022-12-07

    IPC分类号: H04L9/08 H04L9/06

    摘要: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a key generation circuitry and a key-error detection circuitry. The key generation circuitry is arranged operably to realize a key expansion operation for generating multiple round keys based on a root key in an encryption algorithm, where the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round. The error detection circuitry is arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation.

    Method and apparatus for accessing to data in response to power-supply event

    公开(公告)号:US11664056B2

    公开(公告)日:2023-05-30

    申请号:US17723989

    申请日:2022-04-19

    发明人: Wen-Sheng Lin

    IPC分类号: G11C5/14

    CPC分类号: G11C5/141 G11C5/147

    摘要: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: reading a plurality of physical pages of data in a current block from a flash module during a sudden power off recovery procedure; determining whether a power-supply event has occurred according to an error correction result corresponding to read physical pages; reconstructing a first flash-to-host mapping (F2H) table to include physical-to-logical mapping (P2L) information from the 0th page to a page before a last valid page in the current block when the power-supply event has occurred; and programming the reconstructed first F2H table into a location of the flash module.