公开(公告)号：US08281107B2

公开(公告)日：2012-10-02

申请号：US12032709

申请日：2008-02-18

Applicant: Yeon Gon Cho ,  Suk Jin Kim ,  Sang Suk Lee ,  Junhee Kim ,  Jeongwook Kim

Inventor： Yeon Gon Cho ,  Suk Jin Kim ,  Sang Suk Lee ,  Junhee Kim ,  Jeongwook Kim

IPC: G06F15/00

CPC classification number: G06F9/3885 ,  G06F9/3828 ,  G06F9/3877 ,  G06F9/3891 ,  G06F9/3897 ,  G06F15/7867

Abstract: A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core.

Abstract translation: 提供了一种共享粗粒度阵列的方法和使用该方法的处理器。 处理器包括第一处理器核心，其包括执行第一指令集的多个第一功能单元，包括执行第二指令集的多个第二功能单元的第二处理器核心和包括多个第三功能块的粗粒度阵列 执行第一指令集和/或第二指令集的指令的一部分的单元，而不是第一处理器核和/或第二处理器核。

公开(公告)号：US20110219207A1

公开(公告)日：2011-09-08

申请号：US12987391

申请日：2011-01-10

Applicant: Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

Inventor： Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

IPC: G06F15/76 ,  G06F9/22

CPC classification number: G06F9/22 ,  G06F15/76 ,  G06F15/7867

Abstract: A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane.

Abstract translation: 提供了一种用于有效执行向量操作的可重构处理器，以及一种控制可重构处理器的方法。 可重配置处理器基于向量车道配​​置信息将多个处理元件中的至少一个指定为向量车道，并且向指定的向量车道分配向量操作。

公开(公告)号：US07697249B2

公开(公告)日：2010-04-13

申请号：US11646535

申请日：2006-12-28

Applicant: Kyoung-Sik Im ,  Han-Gu Kim ,  Jae-Hyok Ko ,  Il-Hun Son ,  Suk-Jin Kim

Inventor： Kyoung-Sik Im ,  Han-Gu Kim ,  Jae-Hyok Ko ,  Il-Hun Son ,  Suk-Jin Kim

IPC: H02H3/22

CPC classification number: H05K9/0067

Abstract: A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.

Abstract translation: 提供了钳位电路，其可以通过使用已经包括在电路中的晶体管将电路节点处的电压钳位到稳定的电平。 当发生静电放电（ESD）时，钳位电路可以将半导体芯片内的电路的第一节点处的电压钳位到更稳定的水平。 钳位电路可以包括晶体管和电容元件，以存储控制电压以响应于ESD来导通晶体管。

公开(公告)号：US20090228659A1

公开(公告)日：2009-09-10

申请号：US12176605

申请日：2008-07-21

Applicant: Sang Suk LEE ,  Suk Jin Kim ,  Yeon Gon Cho

Inventor： Sang Suk LEE ,  Suk Jin Kim ,  Yeon Gon Cho

IPC: G06F12/08

CPC classification number: G06F12/0846 ,  G06F9/3824

Abstract: A processor and a computing system are provided. A processor includes a processor core, and a buffer memory to read word data from a memory, the read word data including first byte data read by the processor core from the memory, and to store the read word data, wherein the buffer memory determines whether second byte data requested by the processor core is stored in the buffer memory.

Abstract translation: 提供处理器和计算系统。 处理器包括处理器内核和从存储器读取字数据的缓冲存储器，所述读字数据包括处理器核从存储器读取的第一字节数据，并存储读字数据，其中缓冲存储器确定是否 由处理器核心请求的第二字节数据被存储在缓冲存储器中。

公开(公告)号：US20090055626A1

公开(公告)日：2009-02-26

申请号：US12032709

申请日：2008-02-18

Applicant: Yeon Gon CHO ,  Suk Jin Kim ,  Sang Suk Lee ,  Junhee Kim ,  Jeongwook Kim

Inventor： Yeon Gon CHO ,  Suk Jin Kim ,  Sang Suk Lee ,  Junhee Kim ,  Jeongwook Kim

IPC: G06F15/76 ,  G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/3828 ,  G06F9/3877 ,  G06F9/3891 ,  G06F9/3897 ,  G06F15/7867

Abstract: A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core.

Abstract translation: 提供了一种共享粗粒度阵列的方法和使用该方法的处理器。 处理器包括第一处理器核心，其包括执行第一指令集的多个第一功能单元，包括执行第二指令集的多个第二功能单元的第二处理器核心和包括多个第三功能块的粗粒度阵列 执行第一指令集和/或第二指令集的指令的一部分的单元，而不是第一处理器核和/或第二处理器核。

公开(公告)号：US20080140980A1

公开(公告)日：2008-06-12

申请号：US11966832

申请日：2007-12-28

Applicant: Bingfeng Mei ,  Suk Jin Kim ,  Osman Allam

Inventor： Bingfeng Mei ,  Suk Jin Kim ,  Osman Allam

IPC: G06F12/02 ,  G06F9/38

CPC classification number: G06F12/0851 ,  G06F13/1642

Abstract: A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).

Abstract translation: 公开了适用于多处理器系统或阵列的硬件存储器架构或布置。 在一个方面，存储器装置包括功能单元（例如，计算单元）和功能单元访问（用于写入和/或读取访问）的至少一个存储器件之间的至少一个存储器队列。

公开(公告)号：US20070094485A1

公开(公告)日：2007-04-26

申请号：US11542118

申请日：2006-10-04

Applicant: Hong-seok Kim ,  Suk-jin Kim ,  Jeong-wook Kim ,  Soo-jung Ryu

Inventor： Hong-seok Kim ,  Suk-jin Kim ,  Jeong-wook Kim ,  Soo-jung Ryu

IPC: G06F9/44

CPC classification number: G06F9/325 ,  G06F9/3879

Abstract: A data processing system and method. The data processing system includes a processor core that executes a program; a loop accelerator that has an array consisting of a plurality of data processing cells and executes a loop in a program by configuring the array according to a set of configuration bits; and a centralized register file which allows data used in the program execution to be shared by the processor core and the loop accelerator. The loop accelerator divides the configuration of the array into at least three phases according to whether data exchange with the central register file is conducted during the loop execution. Thus, unnecessary occupation of the routing resource, which is used for the data exchange between the loop accelerator and the central register file during the loop execution, can be avoided.

Abstract translation: 一种数据处理系统和方法。 数据处理系统包括执行程序的处理器核心; 循环加速器，其具有由多个数据处理单元组成的阵列，并且通过根据一组配置位配置阵列来执行程序中的循环; 以及允许在程序执行中使用的数据由处理器核和循环加速器共享的集中寄存器文件。 根据在循环执行期间是否进行与中央寄存器文件的数据交换，循环加速器将阵列的配置分为至少三个阶段。 因此，可以避免在循环执行期间用于循环加速器和中央寄存器文件之间的数据交换的路由资源的不必要的占用。

公开(公告)号：US20060089961A1

公开(公告)日：2006-04-27

申请号：US11134615

申请日：2005-05-19

Applicant: Jeong-A Lee ,  Ki-Seon Kim ,  Jeong-Gun Lee ,  Suk-Jin Kim

Inventor： Jeong-A Lee ,  Ki-Seon Kim ,  Jeong-Gun Lee ,  Suk-Jin Kim

IPC: G06F7/50

CPC classification number: G06F7/506 ,  G06F7/507 ,  G06F7/508

Abstract: Disclosed is a mixed-type adder with optimized design costs. The mixed-type adder includes I sub adders, (where, I is a positive number larger than 1). An overall bit width of the mixed-type adder is divided into I bit groups which are respectively allocated to the I sub adders. The I sub adders have different carry propagation schemes and are connected in series through a carry signal.

公开(公告)号：US08954946B2

公开(公告)日：2015-02-10

申请号：US12692735

申请日：2010-01-25

Applicant: Tai-song Jin ,  Dong-kwan Suh ,  Suk-jin Kim

Inventor： Tai-song Jin ,  Dong-kwan Suh ,  Suk-jin Kim

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3846

Abstract: A static branch prediction method and code execution method for a pipeline processor, and a code compiling method for static branch prediction, are provided herein. The static branch prediction method includes predicting a conditional branch code as taken or not-taken, adding the prediction information, converting the conditional branch code into a jump target address setting (JTS) code including target address information, branch time information, and a test code, and scheduling codes in a block. The code may be scheduled into a last slot of the block, and the JTS code may be scheduled into an empty slot after all the other codes in the block are scheduled. When the conditional branch code is predicted as taken in the prediction operation, a target address indicated by the target address information may be fetched at a cycle time indicated by the branch time information.

Abstract translation: 本文提供了一种用于流水线处理器的静态分支预测方法和代码执行方法，以及用于静态分支预测的代码编译方法。 静态分支预测方法包括：预测采取或不采用的条件分支代码，将预测信息相加，将条件分支代码转换成包括目标地址信息，分支时间信息和测试的跳转目标地址设置（JTS）代码 代码和调度代码。 可以将代码调度到块的最后一个时隙中，并且在块中的所有其他代码被调度之后，可以将JTS代码调度到空时隙。 当在预测操作中预测条件分支代码时，可以在由分支时间信息指示的周期时间获取由目标地址信息指示的目标地址。

公开(公告)号：US08813073B2

公开(公告)日：2014-08-19

申请号：US13116601

申请日：2011-05-26

Applicant: Ki-Seok Kwon ,  Suk-Jin Kim ,  Scott Mahlke ,  Yong-Jun Park

Inventor： Ki-Seok Kwon ,  Suk-Jin Kim ,  Scott Mahlke ,  Yong-Jun Park

IPC: G06F9/455 ,  G06F9/46

CPC classification number: G06F8/451 ,  G06F9/5088

Abstract: An apparatus and method capable of reducing idle resources in a multicore device and improving the use of available resources in the multicore device are provided. The apparatus includes a static scheduling unit configured to generate one or more task groups, and to allocate the task groups to virtual cores by dividing or combining the tasks included in the task groups based on the execution time estimates of the task groups. The apparatus also includes a dynamic scheduling unit configured to map the virtual cores to physical cores.

Abstract translation: 提供了一种能够减少多核设备中的空闲资源并改进多核设备中可用资源的使用的装置和方法。 该装置包括：静态调度单元，被配置为生成一个或多个任务组，并且通过基于任务组的执行时间估计来划分或组合包括在任务组中的任务来将任务组分配给虚拟核。 该装置还包括被配置为将虚拟核心映射到物理核心的动态调度单元。