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    Semiconductor device and method for fabricating the same
    41.
    发明授权
    Semiconductor device and method for fabricating the same 有权

    公开(公告)号：US12205909B2

    公开(公告)日：2025-01-21

    申请号：US18138752

    申请日：2023-04-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

    IPC: H01L23/00

    Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

    RESISTIVE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    42.
    发明申请
    RESISTIVE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250017121A1

    公开(公告)日：2025-01-09

    申请号：US18449716

    申请日：2023-08-15

    Applicant: United Microelectronics Corp.

    Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H10N70/00 ,  H10B63/00

    Abstract: A resistive memory structure including a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer, and a protective layer is provided. The dielectric layer is located on the substrate. The conductive plug is located in the dielectric layer. The conductive plug has a protrusion portion located outside the dielectric layer. The resistive memory device is located on the conductive plug. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is located on the conductive plug. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The spacer is located on a sidewall of the resistive memory device. The protective layer is located on a sidewall of the protrusion portion and between the first electrode and the dielectric layer.

    Layout pattern of magnetoresistive random access memory
    46.
    发明授权
    Layout pattern of magnetoresistive random access memory 有权

    公开(公告)号：US12190926B2

    公开(公告)日：2025-01-07

    申请号：US18108025

    申请日：2023-02-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hung-Chan Lin ,  Jia-Rong Wu ,  Yi-Ting Wu

    IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.

    Manufacturing method of semiconductor device
    49.
    发明授权
    Manufacturing method of semiconductor device 有权

    公开(公告)号：US12183809B2

    公开(公告)日：2024-12-31

    申请号：US17673819

    申请日：2022-02-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ta-Wei Chiu ,  Ping-Hung Chiang

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

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