公开(公告)号：US07936615B2

公开(公告)日：2011-05-03

申请号：US12071348

申请日：2008-02-20

Applicant: Jung Sunwoo ,  Yun-Sang Lee

Inventor： Jung Sunwoo ,  Yun-Sang Lee

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4074 ,  G11C11/4096

Abstract: In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied as a word line drive voltage of the memory cell array. The second source voltage has a voltage level higher than a voltage level of the first source voltage. The second source voltage is also applied as a drive voltage of an input/output line driver to drive write data into an input/output line in a write operating mode.

Abstract translation: 在用于在半导体存储器件中提供电源电压的方法中，第一源电压被施加到存储单元阵列的存储单元，作为用于操作耦合到存储单元的读出放大器的单元阵列内部电压。 施加第二源电压作为存储单元阵列的字线驱动电压。 第二源电压具有高于第一源电压的电压电平的电压电平。 第二源电压也作为输入/输出线驱动器的驱动电压施加，以在写操作模式下将写数据驱动到输入/输出线。

公开(公告)号：US07652942B2

公开(公告)日：2010-01-26

申请号：US11757099

申请日：2007-06-01

Applicant: Myeong-o Kim ,  Yun-sang Lee

Inventor： Myeong-o Kim ,  Yun-sang Lee

IPC: G11C7/00

CPC classification number: G11C7/14 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/005

Abstract: A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to the data. The received signals are provided through bit lines connected to the memory cell array. The internal sense amplification unit senses the received reference bit line signal and the data signals and amplifies the sensed signals. The sense amplifier senses data stored in memory cells connected to dummy bit lines of the outmost memory cell array of a semiconductor memory device such that the memory cells that are not used can be used. Accordingly, the design area and cost of the semiconductor memory device can be reduced.

Abstract translation: 读出放大器包括参考信号提供单元和内部检测放大单元。 参考信号提供单元响应于参考控制信号提供参考位线信号。 内部检测放大单元接收对应于数据的参考位线信号和数据信号。 接收的信号通过连接到存储单元阵列的位线来提供。 内部感测放大单元感测接收的参考位线信号和数据信号并放大所感测的信号。 感测放大器感测存储在连接到半导体存储器件的最外存储单元阵列的虚拟位线的存储器单元中的数据，使得可以使用未使用的存储器单元。 因此，可以减少半导体存储器件的设计面积和成本。

公开(公告)号：US20080082871A1

公开(公告)日：2008-04-03

申请号：US11863500

申请日：2007-09-28

Applicant: Hoe-ju CHUNG ,  Yun-sang LEE

Inventor： Hoe-ju CHUNG ,  Yun-sang LEE

IPC: G06F11/277 ,  G06F11/25

CPC classification number: G11C29/14 ,  G11C29/12015 ,  G11C2029/3602

Abstract: A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

Abstract translation: 具有测试模式和正常模式的半导体存储器件包括倍频器和测试命令序列发生器。 倍频器在测试模式下接收测试时钟信号，并产生多个内部测试时钟信号，每个内部测试时钟信号的频率等于正常模式下的操作时钟信号的频率。 测试时钟信号的频率低于操作时钟信号的频率。 测试命令序列发生器响应于测试模式中的内部测试时钟信号而产生至少一个命令信号。 所述至少一个命令信号对应于待测量的半导体存储器件的至少一个操作定时参数。 倍频器可以包括锁相环（PLL）或延迟锁定环（DLL）。

公开(公告)号：US20080056039A1

公开(公告)日：2008-03-06

申请号：US11757099

申请日：2007-06-01

Applicant: Myeong-o Kim ,  Yun-sang Lee

Inventor： Myeong-o Kim ,  Yun-sang Lee

IPC: G11C7/06

CPC classification number: G11C7/14 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/005

Abstract: A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to the data. The received signals are provided through bit lines connected to the memory cell array. The internal sense amplification unit senses the received reference bit line signal and the data signals and amplifies the sensed signals. The sense amplifier senses data stored in memory cells connected to dummy bit lines of the outmost memory cell array of a semiconductor memory device such that the memory cells that are not used can be used. Accordingly, the design area and cost of the semiconductor memory device can be reduced.

Abstract translation: 读出放大器包括参考信号提供单元和内部检测放大单元。 参考信号提供单元响应于参考控制信号提供参考位线信号。 内部检测放大单元接收对应于数据的参考位线信号和数据信号。 接收的信号通过连接到存储单元阵列的位线来提供。 内部感测放大单元感测接收的参考位线信号和数据信号并放大所感测的信号。 感测放大器感测存储在连接到半导体存储器件的最外存储单元阵列的虚拟位线的存储器单元中的数据，使得可以使用未使用的存储器单元。 因此，可以减少半导体存储器件的设计面积和成本。

公开(公告)号：US07067508B2

公开(公告)日：2006-06-27

申请号：US10469198

申请日：2002-03-08

Applicant: Jae Min Jeong ,  Young Ju Kim ,  Yun-Sang Lee ,  Dong Soo Lee ,  June-Key Chung ,  Myung Chul Lee

Inventor： Jae Min Jeong ,  Young Ju Kim ,  Yun-Sang Lee ,  Dong Soo Lee ,  June-Key Chung ,  Myung Chul Lee

IPC: A01N43/00 ,  A61K31/33

CPC classification number: C07D285/00 ,  C07C323/41 ,  C07F13/005 ,  Y02P20/55

Abstract: The present invention relates to a novel diaminedithiol derivative or a pharmaceutically acceptable salt thereof; radiorhenium or radiotechneticum complex thereof; a composition for treating liver cancer comprising the radiorhenium complex and lipiodol; and, a preparative kit of the composition for treating liver cancer.In the composition according to the invention, the diaminedithiol derivative is a novel compound in which long chain alkyl groups were introduced to diaminedithiol, capable of forming a radiorhenium or radiotechnetium complex thereof with an ease and leading to stronger van der Waals bonds with lipiodol. As a result, the complex becomes more stable in a medium, lipiodol, whereby the composition of the invention exhibits a high accumulation rate in liver cancer tissue when injected via hepatic artery, thereby capable of achieving an efficient treatment of liver cancer.

Abstract translation: 本发明涉及一种新的二硫二硫醇衍生物或其药学上可接受的盐; 镭或其无机技术复合物; 用于治疗肝癌的组合物，其包含铑络合物和碘油; 和用于治疗肝癌的组合物的制备试剂盒。 在本发明的组合物中，二硫二硫醇衍生物是一种新的化合物，其中长链烷基被引入到二硫代二醇中，能够容易地形成其镭或镭鎓络合物，并导致与碘碘醇更强的范德华力键。 结果，复合物在培养基，碘油中变得更稳定，由此本发明的组合物通过肝动脉注射时在肝癌组织中表现出高的积累速率，从而能够实现肝癌的有效治疗。

公开(公告)号：US06804163B2

公开(公告)日：2004-10-12

申请号：US10305986

申请日：2002-11-29

Applicant: Yun-sang Lee ,  Jung-bae Lee

Inventor： Yun-sang Lee ,  Jung-bae Lee

IPC: G11C800

CPC classification number: G11C7/12 ,  G11C5/025 ,  G11C7/06 ,  G11C7/10

Abstract: A semiconductor memory device that minimizes chip area is provided. The semiconductor memory device includes local input/output (I/O) lines, global I/O lines, and a memory core that is coupled between a bit line and a complementary bit line. The memory core includes a memory cell array, a bit line equalizer circuit, a PMOS sense amplifier (S/A), a PMOS S/A driving circuit for driving the PMOS S/A, a transmission gate circuit, an NMOS S/A, and an NMOS S/A driving circuit for driving the NMOS S/A. First and second transistors for connecting the local I/O lines to the global I/O lines are installed between adjacent bit lines. The PMOS S/A driving circuit, which is a first driving transistor, and the NMOS S/A driving circuit, which is a second driving transistor, are also installed between adjacent bit lines. Because the semiconductor memory device arranges a PMOS S/A driving circuit, an NMOS S/A driving circuit, and a gating circuit for connecting local I/O lines to global I/O lines, between adjacent bit lines, the chip area is reduced.

Abstract translation: 提供了最小化芯片面积的半导体存储器件。 半导体存储器件包括本地输入/输出（I / O）线，全局I / O线和耦合在位线和互补位线之间的存储器核。 存储器芯包括存储单元阵列，位线均衡器电路，PMOS读出放大器（S / A），用于驱动PMOS S / A的PMOS S / A驱动电路，传输门电路，NMOS S / A 以及用于驱动NMOS S / A的NMOS S / A驱动电路。 用于将本地I / O线连接到全局I / O线的第一和第二晶体管安装在相邻位线之间。 作为第一驱动晶体管的PMOS S / A驱动电路和作为第二驱动晶体管的NMOS S / A驱动电路也安装在相邻位线之间。 由于半导体存储器件在相邻位线之间配置PMOS S / A驱动电路，NMOS S / A驱动电路和用于将本地I / O线连接到全局I / O线的选通电路，芯片面积减小 。

公开(公告)号：US5986917A

公开(公告)日：1999-11-16

申请号：US996806

申请日：1997-12-23

Applicant: Yun-Sang Lee

Inventor： Yun-Sang Lee

IPC: G01R31/26 ,  G01R31/28 ,  G11C8/14 ,  H01L21/66 ,  G11C17/00

CPC classification number: G11C8/14

Abstract: A semiconductor memory device has independently controllable word lines, thereby allowing various background data patterns to be freely written to the memory cells to perform various wafer burn-in tests. This allows the leakage between adjacent memory cells to be efficiently tested by independently controllable word line activation signals, as well as the reliability of bit lines. A wafer burn-in test circuit for performing this improved burn-in test improves the reliability of the device by performing a level transition on the signals that drive the sub word line drivers, thereby eliminating the need to apply a high voltage to one transistor in the sub word line driver.

Abstract translation: 半导体存储器件具有可独立控制的字线，从而允许将各种背景数据模式自由地写入存储器单元以执行各种晶片老化测试。 这允许通过独立可控的字线激活信号以及位线的可靠性来有效地测试相邻存储单元之间的泄漏。 用于进行这种改进的老化测试的晶片老化测试电路通过对驱动子字线驱动器的信号执行电平转换来提高器件的可靠性，从而不需要对一个晶体管施加高电压 子字线驱动。

公开(公告)号：US20140146600A1

公开(公告)日：2014-05-29

申请号：US14077274

申请日：2013-11-12

Applicant: DONG HYUN SOHN ,  CHAN KYUNG KIM ,  YUN SANG LEE

Inventor： DONG HYUN SOHN ,  CHAN KYUNG KIM ,  YUN SANG LEE

IPC: G11C11/16

CPC classification number: G11C11/1697 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

Abstract: A magneto-resistive random access memory (MRAM) comprising an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit comprising a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.

Abstract translation: 包括具有MRAM单元的MRAM单元阵列的磁阻随机存取存储器（MRAM）以及被配置为产生MRAM单元的反向偏置电压的控制和电压产生单元。 所述控制和电压产生单元包括命令解码器，其被配置为响应于从存储器控制器输出的命令产生解码信号;以及电压控制器和发生器，被配置为基于所述解码信号产生具有幅度的所述反向偏置电压，以及 从存储器控制器输出的复位信号。

公开(公告)号：US07844773B2

公开(公告)日：2010-11-30

申请号：US11730275

申请日：2007-03-30

Applicant: Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

Inventor： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

IPC: G06F12/00

CPC classification number: G11C11/406 ,  G11C11/40618

Abstract: A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.

Abstract translation: 提供了具有多于一个组组的半导体存储器件的刷新方法。 刷新方法可以包括将全刷新命令应用于银行组中的一个，当接收到全刷新命令时，确定银行组中的一个是否包括经历刷新操作的存储体，并且基于所述刷新操作执行全刷新操作 决心。

公开(公告)号：US07808858B2

公开(公告)日：2010-10-05

申请号：US11875171

申请日：2007-10-19

Applicant: Yun-sang Lee ,  Jung-bae Lee

Inventor： Yun-sang Lee ,  Jung-bae Lee

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an internal power voltage level. The switching unit transfers a first output of the first power driver to the word line driver in response to a first switching signal and transfers a second output of the second power driver to the word line driver in response to a second switching signal. The word line driver alternately drives a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal.

Abstract translation: 提供了用于驱动字线的方法和电路。 字线驱动电路包括第一和第二电源驱动器，开关单元和字线驱动器。 第一个功率驱动器被驱动到升压电压电平，第二个功率驱动器被驱动到内部电源电压电平。 切换单元响应于第一切换信号将第一功率驱动器的第一输出传送到字线驱动器，并响应于第二切换信号将第二功率驱动器的第二输出传送到字线驱动器。 字线驱动器响应于字线驱动信号交替地驱动字线到第一输出和从开关单元传送的第二输出。