公开(公告)号：US20210042124A1

公开(公告)日：2021-02-11

申请号：US16531295

申请日：2019-08-05

Applicant: Arm Limited

Inventor： Frederic Claude Marie PIRY ,  Thomas Christoper GROCUTT ,  Simon John CRASKE ,  Carlo Dario FANARA ,  Jean Sébastien LEROY

IPC: G06F9/38 ,  G06F9/30

Abstract: Data processing apparatuses, methods of data processing, and non-transitory computer-readable media on which computer-readable code is stored defining logical configurations of processing devices are disclosed. In an apparatus, fetch circuitry retrieves a sequence of instructions and execution circuitry performs data processing operations with respect to data values in a set of registers. An auxiliary execution circuitry interface and a coprocessor interface to provide a connection to a coprocessor outside the apparatus are provided. Decoding circuitry generates control signals in dependence on the instructions of the sequence of instructions, wherein the decoding circuitry is responsive to instructions in a first subset of an instruction encoding space to generate the control signals to control the execution circuitry to perform the first data processing operations, and the decoding circuitry is responsive to instructions in a second subset of the instruction encoding space to generate the control signals in dependence on a configuration condition: to generate the control signals for the auxiliary execution circuitry interface when the configuration condition has a first state; and to generate the control signals for the coprocessor interface when the configuration condition has a second state.

公开(公告)号：US20180314527A1

公开(公告)日：2018-11-01

申请号：US15497461

申请日：2017-04-26

Applicant: ARM Limited

Inventor： Simon John CRASKE

IPC: G06F9/38 ,  G06F9/30

Abstract: Processing circuitry 2 for performing data processing operations includes issue control circuitry to control issue of the processing operations. Validity marking circuitry 22 marks when input operands are valid and available within an issue queue 8, 10, 12. The validity marking circuitry is responsive to a first input operand of the plurality of input operands having a predetermined value to mark a second input operand of the plurality of input operands as meeting its validity condition (i.e. it is possible to determine from the first input operand that the result of the processing operation concerned will be independent of the value of the second input operand and accordingly there is no need to wait for it to actually be available). In order to resolve ordering constraint problems which may be associated with the use of the early valid marking technique separate ordering valid flags may be provided and monitored in respect of at least order-constrained processing operations so as, for example, to enforce load-data to load/store-addressing constraints.

公开(公告)号：US20180074954A1

公开(公告)日：2018-03-15

申请号：US15681467

申请日：2017-08-21

Applicant: ARM LIMITED

Inventor： Simon John CRASKE

IPC: G06F12/02 ,  G06F7/509 ,  G06F5/10

CPC classification number: G06F12/0292 ,  G06F5/10 ,  G06F7/02 ,  G06F7/026 ,  G06F7/509 ,  G06F17/505 ,  G06F2207/382

Abstract: Comparator circuitry comprises carry-save-addition (CSA) circuitry to generate a set of partial sum bits and a set of carry bits in respect of corresponding bit positions in a first input value, a second input value, a carry-in value associated with the first and second input values, and a third input value, the CSA circuitry comprising inverter circuitry to provide a relative inversion between the third input value and the group consisting of the first and second input values; and combiner circuitry to combine the set of partial sum bits, the set of carry bits offset by a predetermined number of bits in a more significant bit direction, the carry-in value and 1, to generate at least a carry output bit; in which the carry output bit is indicative of whether the third input value is greater than the sum of the first and second input values.

公开(公告)号：US20170031685A1

公开(公告)日：2017-02-02

申请号：US15222994

申请日：2016-07-29

Applicant: ARM LIMITED

Inventor： Simon John CRASKE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043

Abstract: An apparatus comprises processing circuitry for processing program instructions according to a predetermined architecture defining a number of architectural registers accessible in response to the program instructions. A set of hardware registers is provided in hardware. A storage capacity of the set of hardware registers is insufficient for storing all the data associated with the architectural registers of the pre-determined architecture. Control circuitry is responsive to the program instructions to transfer data between the hardware registers and at least one register emulating memory location in memory for storing data corresponding to the architectural registers of the architecture.

Abstract translation: 一种装置包括处理电路，用于根据限定响应于该程序指令可访问的多个架构寄存器的预定架构来处理程序指令。 硬件中提供了一组硬件寄存器。 一组硬件寄存器的存储容量不足以存储与预定架构的架构寄存器相关联的所有数据。 控制电路响应于程序指令，以在硬件寄存器和至少一个寄存器之间传送数据，模拟存储器中的存储器位置，用于存储对应于架构的架构寄存器的数据。

公开(公告)号：US20160239405A1

公开(公告)日：2016-08-18

申请号：US15140514

申请日：2016-04-28

Applicant: ARM Limited

Inventor： Michael John WILLIAMS ,  Richard Roy GRISENTHWAITE ,  Simon John CRASKE

IPC: G06F11/36 ,  G06F9/30

CPC classification number: G06F11/3644 ,  G06F9/3004 ,  G06F9/30112 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/45554 ,  G06F11/3648

Abstract: A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state.

Abstract translation: 提供了包括数据处理电路和调试电路的数据处理装置。 当在调试模式下操作时，调试电路控制处理电路的操作。 数据处理电路在进入调试模式时确定数据处理装置的当前操作状态。 数据处理电路根据确定的当前操作状态分配要用作调试指令集的多个指令集中的一个。

公开(公告)号：US20160202977A1

公开(公告)日：2016-07-14

申请号：US14911376

申请日：2014-07-07

Applicant: ARM LIMITED

Inventor： Simon John CRASKE ,  Antony John PENTON

IPC: G06F9/30

CPC classification number: G06F9/3005 ,  G06F9/30145 ,  G06F9/4812 ,  G06F9/4887

Abstract: The execution of time intensive instructions can lead to critical events being responded to late or not being responded to at all. An information processing apparatus comprises processing circuitry (60) for executing instructions comprising one or more time intensive instructions and exception generating circuitry (100) for generating at least one exception for the processing circuitry. The processing circuitry maintains a control value (20) for indicating whether or not the time intensive instructions can be executed. When a time intensive instruction is encountered, if the control value indicates that time intensive instructions cannot be executed then a first exception triggers the processing circuitry to suppress execution of the time intensive instruction. Alternatively, if the control value indicates that time intensive instructions can be executed, then the time intensive instruction is executed.

Abstract translation: 执行时间密集的指令可能导致紧急事件响应迟到或根本没有响应。 一种信息处理设备包括处理电路（60），用于执行包括一个或多个时间密集指令的指令和用于为处理电路产生至少一个异常的异常发生电路（100）。 处理电路保持用于指示是否可以执行时间密集指令的控制值（20）。 当遇到时间密集的指令时，如果控制值指示不能执行时间密集的指令，则第一异常触发处理电路来抑制时间密集指令的执行。 或者，如果控制值指示可以执行时间密集的指令，则执行时间密集的指令。

公开(公告)号：US20160154586A1

公开(公告)日：2016-06-02

申请号：US14926249

申请日：2015-10-29

Applicant: ARM LIMITED

Inventor： Simon John CRASKE

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0673 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/10 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1016 ,  G06F2212/60

Abstract: Memory management is provided within a data processing system 2 which includes a memory protection unit 8 and defines memory regions within the memory address space which extend between base addresses and limit addresses and have respective attributes associated therewith. When a hit occurs within a memory region which is a valid hit, then block data is generated comprising a mask value and a TAG value (derived from the original query address) which may then be used to identify subsequent hits within at least a portion of that region using a bitwise AND. In another embodiment a micro-translation lookaside buffer is reused by the memory protection unit to store page data identifying pages which fall validly within memory regions and may be used to return attribute data for those pages upon subsequent accesses rather than performing the comparison with the base address and the limit addresses.

Abstract translation: 在数据处理系统2内提供存储器管理，数据处理系统2包括存储器保护单元8，并且定义在基地址和限制地址之间延伸的存储器地址空间内的存储区域，并且具有与之相关的各自的属性。 当命中发生在作为有效命中的存储器区域内时，产生包括掩模值和TAG值（从原始查询地址导出）的块数据，该值可以用于识别至少部分内的后续命中 该区域使用按位AND。 在另一个实施例中，微翻译后备缓冲器被存储器保护单元重新使用以存储标识页面的页面数据，该页面有效地落入存储器区域内，并且可以用于在后续访问时返回那些页面的属性数据，而不是执行与基准 地址和限制地址。

公开(公告)号：US20150356029A1

公开(公告)日：2015-12-10

申请号：US14762976

申请日：2013-02-05

Applicant: ARM LIMITED

Inventor： Simon John CRASKE ,  Richard Roy GRISENTHWAITE

IPC: G06F12/14 ,  G06F12/10

CPC classification number: G06F12/1458 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1416 ,  G06F12/1441 ,  G06F12/145 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/651

Abstract: A processing apparatus has a memory protection unit (MPU) 38 and an address translation unit (ATU) 120 which operate concurrently for memory access operations performed by processing circuitry 22. The MPU 38 stores access permission data for corresponding regions of an address space. The ATU 120 stores address translation entries for defining virtual-to-physical mappings for corresponding pages of the address space. In response to a memory access operation specifying a target address, one of the MPU 38 and the ATU 120 is selected to handle the memory access operation based on the target address. If the MPU 38 is selected then the target address is a physical address and the MPU 38 checks access permissions using a corresponding set of permission data. If the ATU 120 is selected then the target address is a virtual address and is translated into a physical address using a corresponding translation entry.

Abstract translation: 处理装置具有对由处理电路22执行的存储器访问操作同时操作的存储器保护单元（MPU）38和地址转换单元（ATU）120。MPU 38存储对于地址空间的相应区域的访问许可数据。 ATU 120存储用于为地址空间的相应页面定义虚拟到物理映射的地址转换条目。 响应于指定目标地址的存储器访问操作，MPU 38和ATU 120中的一个被选择为基于目标地址来处理存储器访问操作。 如果选择了MPU38，则目标地址是物理地址，并且MPU 38使用对应的一组许可数据来检查访问许可。 如果选择ATU 120，则目标地址是虚拟地址，并且使用相应的翻译条目将其翻译成物理地址。

公开(公告)号：US20150347052A1

公开(公告)日：2015-12-03

申请号：US14762229

申请日：2013-02-05

Applicant: ARM LIMITED

Inventor： Richard Roy GRISENTHWAITE ,  Simon John CRASKE ,  Anthony John GOODACRE

IPC: G06F3/06 ,  G06F9/455

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0664 ,  G06F3/0683 ,  G06F9/45545 ,  G06F9/45558 ,  G06F12/1425 ,  G06F12/1483 ,  G06F12/1491 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: A processor (20) is provided with a first memory protection unit (38) applying a first set of permissions and a second memory protection unit (40) applying a second set of permissions. A memory access will only be permitted if both the first set of permissions and the second set of permissions are satisfied. The processor also includes a memory management unit (42) which serves to translate from virtual addresses VA to physical addresses PA. A selectable one of the first memory protection unit (38) and the memory management unit (42) is active at any given time under control of a selection bit set by a hypervisor program (2) executing at an exception level with higher privilege than the exception level at which the guest operating systems execute.

Abstract translation: 处理器（20）设置有应用第一组权限的第一存储器保护单元（38）和应用第二组权限的第二存储器保护单元（40）。 只有满足第一组权限和第二组权限，才允许存储器访问。 处理器还包括用于从虚拟地址VA转换为物理地址PA的存储器管理单元（42）。 第一存储器保护单元（38）和存储器管理单元（42）中的可选择的一个在任何给定时间处于活动状态，在由具有比具有更高特权的特权的异常级别执行的管理程序程序（2）设置的选择位的控制下 客户机操作系统执行的异常级别。

公开(公告)号：US20140075581A1

公开(公告)日：2014-03-13

申请号：US14019580

申请日：2013-09-06

Applicant: ARM LIMITED

Inventor： Thomas Christopher GROCUTT ,  Stuart David BILES ,  Simon John CRASKE

IPC: G06F21/62

CPC classification number: G06F21/629 ,  G06F21/50 ,  G06F21/52 ,  G06F21/54 ,  G06F21/554 ,  G06F21/74 ,  G06F2221/2105

Abstract: A data processing apparatus including processing circuitry having a secure domain and a further different secure domain and a data store for storing data and instructions. The data store includes a plurality of regions each corresponding to a domain, and at least one secure region for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in the further different secure domain and a less secure region for storing less sensitive data. The processing circuitry is configured to verify that a region of the data store storing the program instruction corresponds to a current domain of operation of the processing circuitry and, if not, to verify whether the program instruction includes a guard instruction and, if so, to switch to the domain corresponding to the region of the data store storing the program instruction.

Abstract translation: 一种数据处理装置，包括具有安全域和另一不同安全域的处理电路以及用于存储数据和指令的数据存储。 数据存储器包括多个区域，每个区域各自对应于域，以及至少一个安全区域，用于存储由安全域中操作的数据处理电路可访问的敏感数据，并且不能由在另外不同的安全域中操作的数据处理电路访问 以及用于存储较不敏感数据的较不安全的区域。 处理电路被配置为验证存储程序指令的数据存储区域对应于处理电路的当前操作区域，如果不是，则验证程序指令是否包括保护指令，并且如果是，则 切换到与存储程序指令的数据存储区域对应的域。