公开(公告)号：US20090146704A1

公开(公告)日：2009-06-11

申请号：US11951221

申请日：2007-12-05

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/093

摘要： A delay locked loop (DLL) circuit is provided. The DLL circuit includes a divider, a shift register, a digital-to-analog converter and a voltage controlled delay line. The divider divides an input clock signal to output a reference clock signal. The shift register is triggered by the reference clock signal and outputs a digital signal corresponding to the reference clock signal in accordance with a phase difference between the input clock signal and a feedback clock signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback clock signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed.

摘要翻译： 提供了延迟锁定环（DLL）电路。 DLL电路包括分频器，移位寄存器，数模转换器和电压控制延迟线。 分频器分频输入时钟信号以输出参考时钟信号。 移位寄存器由参考时钟信号触发，并根据输入时钟信号和反馈时钟信号之间的相位差输出与参考时钟信号对应的数字信号。 数模转换器将从移位寄存器输出的数字信号转换为控制电压。 电压控制延迟线根据数模转换器传输的控制电压输出反馈时钟信号。 还公开了一种在延迟锁定环电路中消除输入时钟信号和输出时钟信号之间的抖动和偏移的方法。

公开(公告)号：US08352642B2

公开(公告)日：2013-01-08

申请号：US12938359

申请日：2010-11-02

申请人： Mu-Hsien Hsu ,  Chih-Haur Huang

发明人： Mu-Hsien Hsu ,  Chih-Haur Huang

IPC分类号： G06F3/00 ,  G06F1/00 ,  G06F1/04

CPC分类号： H04N21/4436 ,  G09G2330/021 ,  G09G2370/12 ,  H04N5/63 ,  H04N21/4424

摘要： The present invention provides a method and apparatus of controlling an operational status of an electronic device which receives data through a HDMI port. The present invention determines whether to wake up the electronic device from the power saving mode according to counting numbers generated based on the transitions of signals within a time period.

摘要翻译： 本发明提供一种控制通过HDMI端口接收数据的电子设备的操作状态的方法和装置。 本发明根据在一段时间内基于信号的转变产生的计数数来确定是否将电子设备从省电模式唤醒。

公开(公告)号：US20120105732A1

公开(公告)日：2012-05-03

申请号：US12938359

申请日：2010-11-02

申请人： Mu-Hsien Hsu ,  Chih-Haur Huang

发明人： Mu-Hsien Hsu ,  Chih-Haur Huang

IPC分类号： H04N5/63

CPC分类号： H04N21/4436 ,  G09G2330/021 ,  G09G2370/12 ,  H04N5/63 ,  H04N21/4424

摘要： The present invention provides a method and apparatus of controlling an operational status of an electronic device which receives data through a HDMI port. The present invention determines whether to wake up the electronic device from the power saving mode according to counting numbers generated based on the transitions of signals within a time period.

摘要翻译： 本发明提供一种控制通过HDMI端口接收数据的电子设备的操作状态的方法和装置。 本发明根据在一段时间内基于信号的转变产生的计数数来确定是否将电子设备从省电模式唤醒。

公开(公告)号：US07990303B2

公开(公告)日：2011-08-02

申请号：US12639008

申请日：2009-12-16

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03M1/34 ,  H03M1/38

CPC分类号： H03M1/069 ,  H03M1/12

摘要： An analog-to-digital conversion unit (ADC unit) and an analog-to-digital converting method (ADC method) are provided. The ADC unit has a plurality of sub analog-to-digital converters and an encoding unit. Each of the employed sub analog-to-digital converters is coupled to two threshold voltages non-successive in terms of levels arrangement, compares the input voltage with the two threshold voltages and outputs two bits according to the comparison results. In this way, the difference between the two threshold voltages coupled by each of the sub analog-to-digital converters can be larger, which is advantageous in advancing the analog-to-digital converting accuracy.

摘要翻译： 提供了模数转换单元（ADC单元）和模数转换方法（ADC方法）。 ADC单元具有多个子模数转换器和编码单元。 每个采用的子模数转换器在电平排列方面被耦合到两个不连续的阈值电压，将输入电压与两个阈值电压进行比较，并根据比较结果输出两个位。 以这种方式，由每个子模数转换器耦合的两个阈值电压之间的差可以更大，这有利于提高模数转换精度。

公开(公告)号：US20110140947A1

公开(公告)日：2011-06-16

申请号：US12639008

申请日：2009-12-16

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03M1/12

CPC分类号： H03M1/069 ,  H03M1/12

摘要： An analog-to-digital conversion unit (ADC unit) and an analog-to-digital converting method (ADC method) are provided. The ADC unit has a plurality of sub analog-to-digital converters and an encoding unit. Each of the employed sub analog-to-digital converters is coupled to two threshold voltages non-successive in terms of levels arrangement, compares the input voltage with the two threshold voltages and outputs two bits according to the comparison results. In this way, the difference between the two threshold voltages coupled by each of the sub analog-to-digital converters can be larger, which is advantageous in advancing the analog-to-digital converting accuracy.

摘要翻译： 提供了模数转换单元（ADC单元）和模数转换方法（ADC方法）。 ADC单元具有多个子模数转换器和编码单元。 每个采用的子模数转换器在电平排列方面被耦合到两个不连续的阈值电压，将输入电压与两个阈值电压进行比较，并根据比较结果输出两个位。 以这种方式，由每个子模数转换器耦合的两个阈值电压之间的差可以更大，这有利于提高模数转换精度。

公开(公告)号：US20110140939A1

公开(公告)日：2011-06-16

申请号：US12639009

申请日：2009-12-16

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03M1/00

CPC分类号： G11C27/026 ,  H03M1/1295

摘要： A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit.

摘要翻译： 提供了采样保持电路和采样和保持信号的方法。 采样保持电路包括采样单元，直流（DC）电压消除单元和保持单元。 当采样保持电路处于第一状态时，采样单元对输入信号进行采样，直流电压消除单元降低由采样单元采样的输入信号中的直流电压的预定百分比。 当采样保持电路处于第二状态时，直流电压消除单元消除直流电压的剩余百分比，并且保持单元输出由采样单元采样的输入信号中的交流（AC）信号。

公开(公告)号：US07916819B2

公开(公告)日：2011-03-29

申请号：US11907175

申请日：2007-10-10

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/0996

摘要： A receiver system is provided. The receiver system includes a control unit for outputting a control signal and a selective signal, a PLL unit for generates PLL clock signals based on an initial clock signal, a phase select unit for selecting one of the PLL clock signals as a base clock signal according to the selective signal, a DLL unit for generating DLL clock signals based on the base clock signal, a sampling clock unit for generating left and right clock signals based on the DLL clock signals and a data latch unit for sampling bit data according to the left, DLL, and right clock signals to obtain left, middle and right data, which are feedback to the control unit for outputting the control signal and the selective signal to adjust the left, DLL and right clock signals or select the base clock signal for next bit data.

摘要翻译： 提供接收机系统。 接收机系统包括用于输出控制信号和选择信号的控制单元，用于基于初始时钟信号产生PLL时钟信号的PLL单元，用于选择PLL时钟信号之一作为基本时钟信号的相位选择单元， 基于所述基本时钟信号生成DLL时钟信号的DLL单元，基于所述DLL时钟信号生成左右时钟信号的采样时钟单元，以及根据左侧的位数据采样的数据锁存单元 ，DLL和右时钟信号，以获得左，中，右数据，其反馈到控制单元以输出控制信号和选择信号以调整左，右和右时钟信号或选择下一个基本时钟信号 位数据。

公开(公告)号：US20100309038A1

公开(公告)日：2010-12-09

申请号：US12479901

申请日：2009-06-08

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03M1/38 ,  H03M1/12 ,  H03M1/00

CPC分类号： H03M1/0607 ,  H03M1/167 ,  H03M1/44

摘要： An analog to digital converter is provided. The converter comprises a first stage, an adjustment unit and a digital error correction logic. The first stage has a first sensing range and receives a first voltage to generate a first digital code. The adjustment unit adjusts the first sensing range of the first stage. The digital error correction logic receives and corrects the first digital code to generate a digital code corresponding to the first voltage.

摘要翻译： 提供了模数转换器。 转换器包括第一级，调整单元和数字纠错逻辑。 第一级具有第一感测范围并且接收第一电压以产生第一数字码。 调整单元调整第一级的第一感测范围。 数字纠错逻辑接收和校正第一数字码以产生对应于第一电压的数字码。

公开(公告)号：US20100201553A1

公开(公告)日：2010-08-12

申请号：US12368593

申请日：2009-02-10

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03M1/20

CPC分类号： H03M1/0641 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/207

摘要： A method for enhancing resolution of digital signals converted from analog signals is provided. The method includes the steps of: converting an analog input signal into N-bit digital outputs, where N is a positive integer; interpolating the N-bit digital outputs to add one or more least significant bit orders for the N-bit digital outputs; generating one or more dither values as least significant bits corresponding to the least significant bit orders; and superimposing the dither values on the interpolation of the N-bit digital outputs. An A/D converter is also disclosed herein.

摘要翻译： 提供了一种用于增强从模拟信号转换的数字信号分辨率的方法。 该方法包括以下步骤：将模拟输入信号转换成N位数字输出，其中N是正整数; 内插N位数字输出，为N位数字输出增加一个或多个最低有效位指令; 产生一个或多个抖动值作为对应于最低有效位顺序的最低有效位; 并将抖动值叠加在N位数字输出的内插上。 本文还公开了A / D转换器。

公开(公告)号：US07733139B2

公开(公告)日：2010-06-08

申请号：US12010554

申请日：2008-01-25

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891

摘要： A delay locked loop circuit includes a phase-frequency detector, a sampler, a charge pump, a bias generator and a voltage-controlled element. The phase-frequency detector outputs at least one difference signal by detecting a phase difference between an input clock signal and a feedback clock signal. The sampler outputs at least one sampled signal by delaying the difference signal in accordance with the input clock signal. The charge pump generates a control voltage in accordance with the sampled signal. The bias generator generates at least one bias voltage in accordance with the control voltage. The voltage-controlled element is controlled with the bias voltage to output the feedback clock signal to the phase-frequency detector in accordance with the input clock signal. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed.

摘要翻译： 延迟锁定环电路包括相位频率检测器，采样器，电荷泵，偏置发生器和电压控制元件。 相位 - 频率检测器通过检测输入时钟信号和反馈时钟信号之间的相位差来输出至少一个差分信号。 采样器通过根据输入时钟信号延迟差分信号来输出至少一个采样信号。 电荷泵根据采样信号产生一个控制电压。 偏置发生器根据控制电压产生至少一个偏置电压。 电压控制元件由偏置电压控制，以根据输入时钟信号将反馈时钟信号输出到相位检波器。 还公开了一种在延迟锁定环电路中消除输入时钟信号和输出时钟信号之间的抖动和偏移的方法。