公开(公告)号：US11714480B2

公开(公告)日：2023-08-01

申请号：US17499723

申请日：2021-10-12

Applicant: Apple Inc.

Inventor： Jay B. Fletcher ,  Karthik Manickam ,  Bo Yang ,  Vincent R. von Kaenel ,  Shawn Searles ,  Hubert Attah ,  Nir Dahan ,  Olivier Girard

IPC: G06F1/32 ,  G06F1/3296 ,  G01R31/28 ,  G06F1/3206

CPC classification number: G06F1/3296 ,  G01R31/2851 ,  G06F1/3206

Abstract: A voltage regulator circuit included in a computer system may generate a voltage level on a power supply signal using a source power supply signal and based initial values of one or more operation parameters derived from wafer-level test data. One or more operation characteristics of the voltage regulator circuit may be sampled, by a measurement circuit, at multiple time points to generated measurement data. A control circuit may adapt operation of the voltage regulator circuit based on the measurement data.

公开(公告)号：US11467614B2

公开(公告)日：2022-10-11

申请号：US17017639

申请日：2020-09-10

Applicant: Apple Inc.

Inventor： Ruopeng Wang ,  Jay B. Fletcher

IPC: G05F1/575 ,  G05F1/565

Abstract: A voltage regulator circuit includes a switch device that is coupled between an input power supply and a regulated power supply node. The voltage regulator circuit adjusts a value of a current flowing from the input power supply to the regulated power supply node by modifying a voltage level of a control node coupled to the switch device. A control circuit adjusts the voltage level of the control node using an error signal based on a comparison of the voltage level of the regulated power supply node and a reference voltage. To improve the response time of the voltage regulator circuit to changes in load current, the control circuit additionally sources current to and/or sinks current from the control node based on a voltage level of the control node.

公开(公告)号：US11431250B2

公开(公告)日：2022-08-30

申请号：US17140919

申请日：2021-01-04

Applicant: Apple Inc.

Inventor： Jay B. Fletcher

IPC: H02M3/158

Abstract: A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.

公开(公告)号：US11133663B2

公开(公告)日：2021-09-28

申请号：US15849222

申请日：2017-12-20

Applicant: Apple Inc.

Inventor： Nathan F. Hanagami ,  Jay B. Fletcher

IPC: H02H3/18 ,  H02H9/02 ,  H03K17/0812 ,  G05F1/575 ,  H03K17/082 ,  G05F1/46

Abstract: A circuit and method for protecting from reverse current is disclosed. A reverse current protection circuit is coupled to a pass transistor of power circuitry (e.g., a power switch or voltage regulator), the pass transistor being coupled between first and second voltage nodes, the first voltage node being coupled to a power supply circuit. The reverse current protection circuit includes a sensing circuit that is configured to sense an amount of reverse current flowing through the pass transistor (from the second voltage node to the first voltage node). Responsive to the amount of reverse current exceeding a threshold value, the reverse current sensing circuit activates a shunt circuit, which redirects at least some of the reverse current to a reference node (e.g., ground).

公开(公告)号：US10886851B1

公开(公告)日：2021-01-05

申请号：US16570805

申请日：2019-09-13

Applicant: Apple Inc.

Inventor： Jay B. Fletcher

IPC: H02M3/158

Abstract: A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.

公开(公告)号：US10146240B1

公开(公告)日：2018-12-04

申请号：US15886700

申请日：2018-02-01

Applicant: Apple Inc.

Inventor： Ruopeng Wang ,  Dashun Xue ,  Jiandong Jiang ,  Jay B. Fletcher

IPC: G05F3/16 ,  G05F1/575 ,  H02M7/10 ,  G05F3/24

Abstract: A voltage regulator having a pre-regulator circuit is disclosed. A low dropout (LDO) voltage regulator includes an amplifier circuit, a current buffer circuit, and a pre-regulator circuit. The current buffer circuit includes a transistor having a gate terminal coupled to the amplifier output. The current buffer provides a current based at least in part on the output signal generated by the amplifier. The pre-regulator circuit is coupled to provide a dynamic supply voltage to the current buffer. They dynamic supply voltage depends at least in part on a fixed supply voltage provided thereto, as well as the output voltage provided by the LDO voltage regulator.

公开(公告)号：US10122269B2

公开(公告)日：2018-11-06

申请号：US15402827

申请日：2017-01-10

Applicant: Apple Inc.

Inventor： Fabio Gozzini ,  Jay B. Fletcher ,  Shawn Searles ,  Sanjay Pant

IPC: G05F1/40 ,  H02M3/156 ,  H02M1/08 ,  H02M3/158 ,  H02M1/00

Abstract: A system that includes a regulator circuit is disclosed. The regulator circuit includes first and second phase units whose outputs are coupled to a power supply node of a circuit block, via respective coupled inductors. The first phase unit may initiate a charge cycle of the power supply node in response to assertion of a clock signal and generate a compensated current using currents measure through both inductors and the clock signal. In response to a determination that the compensated current is greater than a demand current generated using a voltage level of the power supply node and a reference voltage, the first phase unit may halt the charge cycle.

公开(公告)号：US09989981B1

公开(公告)日：2018-06-05

申请号：US15625776

申请日：2017-06-16

Applicant: Apple Inc.

Inventor： Dingkun Du ,  Jay B. Fletcher

IPC: G05F1/595 ,  H03F3/16 ,  G05F1/46

CPC classification number: G05F1/595 ,  G05F1/461 ,  G05F1/563 ,  G05F1/61 ,  H03F3/16 ,  H03F2200/69 ,  H03F2200/72 ,  H03F2200/75

Abstract: A voltage regulator is disclosed. The voltage regulator is cascaded, including first and second stages. The first stage may be a capacitor-less first stage that includes a source follower implemented with a first PMOS transistor, with the first PMOS transistor receiving a first reference voltage on its respective gate terminal. The first stage is coupled to receive a first voltage from an external voltage supply, and to provide a second voltage to the second stage. The second stage may be directly and exclusively coupled to the first stage, with no capacitor or connection for one coupled to the first stage output. The second stage may provide an output voltage, on an output node, with the output voltage being less than the second voltage.

公开(公告)号：US20180083534A1

公开(公告)日：2018-03-22

申请号：US15403255

申请日：2017-01-11

Applicant: Apple Inc.

Inventor： Sanjay Pant ,  Fabio Gozzini ,  Jay B. Fletcher ,  Shawn Searles

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M3/158 ,  H02M1/08 ,  H02M3/1584 ,  H02M2001/0009 ,  H02M2003/1586

Abstract: A system that includes a regulator unit is disclosed. The regulator unit includes first and second phase units whose outputs are coupled to through first and second coupled inductors, respectively, to a power supply node of a circuit block. The first phase unit may be configured to discharge, for a first period of time, the power supply node through the first inductor in response to determining a sense current is greater than a demand current. The operation of the second phase unit may follow that of the first phase unit after a second period of time has elapsed.

公开(公告)号：US09843330B1

公开(公告)日：2017-12-12

申请号：US15272526

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Hubert Attah ,  Jay B. Fletcher ,  Erick O. Torres ,  Fabio Gozzini

IPC: H03K21/02 ,  H03K19/21

CPC classification number: H03K21/026 ,  H02M3/157 ,  H03K19/21

Abstract: An apparatus is disclosed, including a driver circuit, a comparator circuit, and a counter circuit. The driver circuit may be configured to source a current to a load circuit. The comparator circuit may be configured to perform a comparison of a reference voltage to a voltage across the load circuit. The counter circuit may be configured to modify a digital count value based on the comparison. The driver circuit may be further configured to adjust a value of the current using the digital count value.