公开(公告)号：US09589601B2

公开(公告)日：2017-03-07

申请号：US14659270

申请日：2015-03-16

Applicant: ARM Limited ,  The Regents of the University of Michigan

Inventor： Mahmood Khayatzadeh ,  Massimo Bruno Alioto ,  David Blaauw ,  Dennis Michael Chen Sylvester ,  Fakhruddin Ali Bohra

IPC: G11C7/00 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/18 ,  G11C8/16 ,  G11C11/419 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/002 ,  G11C2207/005

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Abstract translation: 本文描述的各种实施方式可以涉及并且可以涉及使用拓扑配置的集成电路的电路。 例如，在一个实现中，这种电路可以包括具有多个存储器单元的存储器阵列。 这种电路还可以包括耦合到存储器阵列并被配置为放大从存储器阵列接收的差分电压电平的一个或多个可重新配置的读出放大器器件。 可重构感测放大器装置可以包括多个读出放大器电路，其被配置为布置成多个拓扑结构中的一种，其中拓扑结构包括并行配置和交叉并行配置。 可重构感测放大器装置还可以包括一个或多个开关，其被配置为基于一个或多个控制位将多个读出放大器电路设置成多个拓扑结构。

公开(公告)号：US09407265B2

公开(公告)日：2016-08-02

申请号：US14088570

申请日：2013-11-25

Applicant: ARM LIMITED

Inventor： Srinivasan Srinath ,  Ambica Ashok ,  Fakhruddin Ali Bohra

IPC: H03K19/096 ,  H03K19/017 ,  H03K19/00 ,  H03K19/094 ,  G11C11/419 ,  G11C7/12

CPC classification number: H03K19/01721 ,  G11C7/12 ,  G11C11/419 ,  H03K19/0013 ,  H03K19/09429 ,  H03K19/0963

Abstract: An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption.

Abstract translation: 集成电路具有信号辅助电路，用于帮助将信号线上的信号拉向逻辑低或高信号电平。 信号辅助电路包括第一和第二辅助电路。 第一辅助电路在信号的上拉转换之后将信号线耦合到逻辑高信号电平，并且在下拉转换之后提供浮动信号电平，而第二辅助电路在上拉跃迁之后提供浮动信号电平，并提供逻辑 下拉转换后的低信号电平。 通过提供互补的第一和第二辅助电路，每个电路可以针对相反的过渡进行优化，以实现改进的性能或功耗。

公开(公告)号：US12230317B2

公开(公告)日：2025-02-18

申请号：US18369794

申请日：2023-09-18

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Vidit Babbar

IPC: G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

公开(公告)号：US12159664B2

公开(公告)日：2024-12-03

申请号：US16709665

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa

IPC: G11C11/419 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

公开(公告)号：US11222670B2

公开(公告)日：2022-01-11

申请号：US16709687

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Cyrille Nicolas Dray ,  Ashish Bhardwaj ,  Durgesh Kumar Dubey

IPC: G11C7/00 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

Abstract: Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.

公开(公告)号：US20210335397A1

公开(公告)日：2021-10-28

申请号：US16860764

申请日：2020-04-28

Applicant: Arm Limited

Inventor： Fakhruddin Ali Bohra ,  Lalit Gupta ,  Shri Sagar Dwivedi

IPC: G11C7/10

Abstract: Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first set of multiplexers that receives column data from the array of memory cells and provides first multiplexed output data. The device may include output interface circuitry coupled to the output circuitry, and the output interface circuitry may have a second set of multiplexers that receives the first multiplexed output data from the output circuitry and selectively provides second multiplexed output data based on a configurable mode of multiplexed operation.

公开(公告)号：US10755774B2

公开(公告)日：2020-08-25

申请号：US16820487

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US20200014373A1

公开(公告)日：2020-01-09

申请号：US16026946

申请日：2018-07-03

Applicant: Arm Limited

Inventor： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

IPC: H03K5/06 ,  G06F12/0804

Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

公开(公告)号：US20200005836A1

公开(公告)日：2020-01-02

申请号：US16024449

申请日：2018-06-29

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Gaurav Rattan Singla

IPC: G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/14

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

公开(公告)号：US20190325949A1

公开(公告)日：2019-10-24

申请号：US15960482

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.