Pixel drive circuit, pixel unit, driving method, array substrate, and display apparatus

    公开(公告)号:US11514844B2

    公开(公告)日:2022-11-29

    申请号:US17424408

    申请日:2020-09-10

    Abstract: A pixel drive circuit includes a data write sub-circuit, an input and read sub-circuit, a drive sub-circuit, and a first output control sub-circuit. The data write sub-circuit is configured to transmit data signals input from a first data voltage terminal at different times to a first node. The input and read sub-circuit is configured to: transmit a signal of a signal transmission terminal to a second node in a write period, and transmit an electrical signal of the second node to the signal transmission terminal in a threshold voltage read period. The drive sub-circuit is configured to output a drive signal. The first output control sub-circuit is configured to: be coupled to an element to be driven, and transmit the drive signal output by the drive sub-circuit to the element to be driven.

    Display substrate, display panel and display apparatus

    公开(公告)号:US11348523B2

    公开(公告)日:2022-05-31

    申请号:US17271737

    申请日:2020-07-29

    Abstract: A display substrate, includes: a plurality of pixel driving circuits; a plurality of groups of light-emitting driving signal lines, wherein each driving signal line group of the plurality of groups of light-emitting driving signal lines includes a plurality of light-emitting driving signal lines; and a plurality of pixel circuit multiplexing units coupled to the plurality of pixel driving circuits, respectively, wherein each pixel circuit multiplexing unit includes N light-emitting units coupled to one of the plurality of pixel driving circuits and a group of light-emitting driving signal line.

    Array substrate, driving method thereof, and display apparatus

    公开(公告)号:US12073772B2

    公开(公告)日:2024-08-27

    申请号:US17511335

    申请日:2021-10-26

    Abstract: Disclosed is an array substrate including multiple first selection circuits with each including at least two first selection transistors and at least two first anticreeping transistors. Each first selection transistor is connected with one first anticreeping transistor in series. When the first selection transistor is turned on by a first turn-on signal from a first control signal terminal, the first anticreeping transistor is turned on by a second turn-on signal from a second control signal terminal. When the first selection transistor is turned off by a first turn-off signal from the first control signal terminal, the first anticreeping transistor is turned off to make the first selection transistors and the data signal terminal disconnected, by a second turn-off signal from the second control signal terminal. A voltage of the first turn-off signal is greater than a voltage of the second turn-off signal.

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