公开(公告)号：US07023042B2

公开(公告)日：2006-04-04

申请号：US10755498

申请日：2004-01-12

申请人： Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/88 ,  H01L27/10814 ,  H01L27/10852

摘要： A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.

摘要翻译： 已经开发了用于形成具有增加的表面积的DRAM叠层电容器结构的工艺。 该工艺在用于限定存储节点结构的干蚀刻过程中，在多晶硅存储节点结构的侧面形成横向凹槽。 这些凹槽是选择性地和侧向地形成在离子植入的静脉中，这些静脉又通过一系列离子注入步骤而被放置在本征多晶硅层中的各种深度处，每个离子注入步骤以特定的注入能量进行。 存储节点结构的同位素组分定义了干蚀刻过程，选择性地以高于离子植入的静脉之间的聚合物的非离子注入区域的速率以更高的速率蚀刻高度掺杂的离子植入的静脉，产生颈缩轮廓， 存储节点结构，由于形成横向槽而具有增加的表面积。

公开(公告)号：US06828237B1

公开(公告)日：2004-12-07

申请号：US10662069

申请日：2003-09-11

申请人： Bor-Wen Chan ,  Fang-Cheng Chen ,  Hsien-Kuang Chiu ,  Yuan-Hung Chiu ,  Han-Jan Tao

发明人： Bor-Wen Chan ,  Fang-Cheng Chen ,  Hsien-Kuang Chiu ,  Yuan-Hung Chiu ,  Han-Jan Tao

IPC分类号： H01L21311

CPC分类号： H01L21/0338 ,  H01L21/28123 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823437

摘要： A plasma etch method for forming a patterned target layer within a microelectrcnic product forms an etch residue layer adjoining a patterned mask layer formed upon a blanket target layer. After removing the patterned mask layer, the etch residue layer is laterally increased to form a laterally increased etch residue layer. The laterally increased etch residue layer is employed as an etch mask for forming the patterned target layer from the blanket target layer. The method is particularly useful for forming gate electrodes within semiconductor products.

摘要翻译： 用于在微电子产品内形成图案化目标层的等离子体蚀刻方法形成邻接形成在覆盖目标层上的图案化掩模层的蚀刻残余层。 在去除图案化的掩模层之后，蚀刻残余层被横向增加以形成横向增加的蚀刻残留层。 使用横向增加的蚀刻残留层作为用于从覆盖目标层形成图案化目标层的蚀刻掩模。 该方法对于在半导体产品中形成栅电极特别有用。

公开(公告)号：US06812044B2

公开(公告)日：2004-11-02

申请号：US10324465

申请日：2002-12-19

申请人： Hsien-Kuang Chiu ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Hsien-Kuang Chiu ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L2100

CPC分类号： H01J37/32935 ,  H01L21/67069 ,  H01L21/67253

摘要： A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either terminating the plasma process or modifying the plasma process in progress to re-establish the plasma parameters within the parameter specifications. The plasma parameters may be measured by the self-excited electron resonance spectroscopy (SEEKS) technique or by microwave interferometry.

摘要翻译： 一种用于在诸如等离子体蚀刻工艺的等离子体工艺期间监测等离子体参数的方法，将测量的等离子体参数与预定参数规格进行比较，以及终止等离子体处理或修改正在进行的等离子体处理，以重新建立参数内的等离子体参数 规格。 等离子体参数可以通过自激电子共振光谱（SEEKS）技术或通过微波干涉测量来测量。

公开(公告)号：US06352919B1

公开(公告)日：2002-03-05

申请号：US09620033

申请日：2000-07-20

申请人： Yeur-Luen Tu ,  Bor-Wen Chan ,  Yuan-Hung Liu

发明人： Yeur-Luen Tu ,  Bor-Wen Chan ,  Yuan-Hung Liu

IPC分类号： H01L214763

CPC分类号： H01L21/76802 ,  H01L21/76801

摘要： A method of fabricating a borderless via is disclosed. A semiconductor substrate having a first dielectric layer thereon is provided. Next, a first conductive structure and a second conductive structure whose area is much smaller than said first conductive structure are formed on said first dielectric layer. After that, a second dielectric layer with an uneven surface is formed. Then, a planarizing layer is coated over said second dielectric layer to fill said uneven surface. Next, an etch back process is used to create a etching stop layer consisting of a portion of second dielectric layer. Subsequently, a third dielectric layer is formed over said second dielectric layer followed by selectively etching said third dielectric layer until said second dielectric layer is exposed to create a borderless via.

摘要翻译： 公开了制造无边界通孔的方法。 提供其上具有第一介电层的半导体衬底。 接下来，在所述第一介电层上形成面积比所述第一导电结构小得多的第一导电结构和第二导电结构。 之后，形成具有不平坦表面的第二电介质层。 然后，在所述第二电介质层上涂覆平坦化层以填充所述不平坦表面。 接下来，使用回蚀工艺来产生由第二介电层的一部分组成的蚀刻停止层。 随后，在所述第二电介质层上形成第三电介质层，随后选择性地蚀刻所述第三电介质层，直到所述第二电介质层暴露以形成无边界通孔。

公开(公告)号：US6110837A

公开(公告)日：2000-08-29

申请号：US301481

申请日：1999-04-28

申请人： Kung Linliu ,  Bor-Wen Chan

发明人： Kung Linliu ,  Bor-Wen Chan

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/00

CPC分类号： H01L21/0274 ,  H01L21/0337 ,  H01L21/0338

摘要： The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has a critical dimension, which the conventional lithography process can make. Subsequently, a hard mask of half critical dimension is formed in the silicon oxide layer by using the photoresist layer as an etching mask. After the oxide hard mask is formed, the gate structure of half critical dimension is formed by using the oxide hard mask.

摘要翻译： 本发明公开了一种在基板上形成半临界尺寸的硬掩模的方法。 为集成电路的基底提供基板。 在基板上形成氧化硅层。 在氧化硅层上形成光致抗蚀剂层，其具有常规光刻工艺可制造的临界尺寸。 随后，通过使用光致抗蚀剂层作为蚀刻掩模，在氧化硅层中形成半临界尺寸的硬掩模。 在形成氧化物硬掩模之后，通过使用氧化物硬掩模形成半临界尺寸的栅极结构。