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    Method of fabricating a borderless via
    1.
    发明授权
    Method of fabricating a borderless via 有权
    制造无边界通孔的方法

    公开(公告)号：US06352919B1

    公开(公告)日：2002-03-05

    申请号：US09620033

    申请日：2000-07-20

    申请人： Yeur-Luen Tu ,  Bor-Wen Chan ,  Yuan-Hung Liu

    发明人： Yeur-Luen Tu ,  Bor-Wen Chan ,  Yuan-Hung Liu

    IPC分类号： H01L214763

    CPC分类号： H01L21/76802 ,  H01L21/76801

    摘要： A method of fabricating a borderless via is disclosed. A semiconductor substrate having a first dielectric layer thereon is provided. Next, a first conductive structure and a second conductive structure whose area is much smaller than said first conductive structure are formed on said first dielectric layer. After that, a second dielectric layer with an uneven surface is formed. Then, a planarizing layer is coated over said second dielectric layer to fill said uneven surface. Next, an etch back process is used to create a etching stop layer consisting of a portion of second dielectric layer. Subsequently, a third dielectric layer is formed over said second dielectric layer followed by selectively etching said third dielectric layer until said second dielectric layer is exposed to create a borderless via.

    摘要翻译： 公开了制造无边界通孔的方法。 提供其上具有第一介电层的半导体衬底。 接下来，在所述第一介电层上形成面积比所述第一导电结构小得多的第一导电结构和第二导电结构。 之后，形成具有不平坦表面的第二电介质层。 然后，在所述第二电介质层上涂覆平坦化层以填充所述不平坦表面。 接下来，使用回蚀工艺来产生由第二介电层的一部分组成的蚀刻停止层。 随后，在所述第二电介质层上形成第三电介质层，随后选择性地蚀刻所述第三电介质层，直到所述第二电介质层暴露以形成无边界通孔。

    SEMICONDUCTOR METHODS
    3.
    发明申请
    SEMICONDUCTOR METHODS 有权
    半导体方法

    公开(公告)号：US20090130814A1

    公开(公告)日：2009-05-21

    申请号：US12357661

    申请日：2009-01-22

    申请人： Yuan-Hung LIU ,  Ming Chyi Liu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chai-Shiung Tsai

    发明人： Yuan-Hung LIU ,  Ming Chyi Liu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chai-Shiung Tsai

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02274 ,  H01L21/02115 ,  H01L21/28273 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3146 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/14632 ,  H01L27/14687 ,  H01L28/91 ,  H01L29/42328 ,  H01L29/7881

    摘要： A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.

    摘要翻译： 一种方法包括在形成在衬底上的第一电介质层上形成无定形碳层，在非晶碳层上形成第二电介质层; 以及通过第一蚀刻工艺在所述非晶碳层和所述第二介电层内形成开口，以部分地暴露所述第一介电层的顶表面。 在第二电介质层上并在开口内形成基本上共形的含金属层。 去除第二电介质层和一部分含金属层。 通过含氧等离子体工艺除去无定形碳层以暴露第一介电层的顶表面。 在含金属层的上方形成有绝缘层，在绝缘层上形成第二含金属层，形成电容器。

    Magnetic memory cells and manufacturing methods
    5.
    发明申请
    Magnetic memory cells and manufacturing methods 有权
    磁记忆体和制造方法

    公开(公告)号：US20070096230A1

    公开(公告)日：2007-05-03

    申请号：US11610760

    申请日：2006-12-14

    申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L43/00 ,  H01L29/82

    CPC分类号： H01L43/12 ,  H01L27/228

    摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

    摘要翻译： 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。

    Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence
    7.
    发明授权
    Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence 失效
    在外径（OD）和强栅栏上制作用于宽过度蚀刻窗口的字线间隔件的方法

    公开(公告)号：US06869837B1

    公开(公告)日：2005-03-22

    申请号：US10758316

    申请日：2004-01-15

    申请人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

    发明人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

    IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer. Then etching: away the exposed portions of the conductive layer over the substrate; and through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.

    摘要翻译： 一种制造字线间隔物的方法，包括以下步骤。 提供了具有形成在其上的初始分离栅闪存结构的衬底。 导电层形成在衬底和初生分裂栅极闪存结构之上。 所述导电层具有：上部分裂栅极闪存结构上方的上部和下部垂直部分; 并且在基底上下方水平部分。 在导电层之上形成双层氧化物层，并且在导电层的上部上具有更大的厚度。 将氧化层部分地回蚀刻以从导电层的下部水平部分上方至少去除氧化物层，以暴露导电层的下面部分。 然后蚀刻：将导电层的暴露部分远离衬底; 并且通过至少一部分减薄的氧化物层并进入导电层的暴露的下面的部分，以暴露初步分离栅闪存结构的一部分并且形成邻近先驱分离栅闪存的字线间隔物 结构体。

    HDP gap-filling process for structures with extra step at side-wall
    8.
    发明授权
    HDP gap-filling process for structures with extra step at side-wall 失效
    HDP间隙填充过程，用于侧壁额外加工的结构

    公开(公告)号：US06780731B1

    公开(公告)日：2004-08-24

    申请号：US10225803

    申请日：2002-08-22

    申请人： Yeur-Luen Tu ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Yuan-Hung Liu

    发明人： Yeur-Luen Tu ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Yuan-Hung Liu

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon first layer, an oxide second layer and a nitride third layer, wherein the nitride layer is pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without dam aging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the side walls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio and low bias power to form a layer with an overhang at the upper surface of the trench. This deposition if followed by a sputtering process to form an enlarged opening in that overhang. This approach is found to prevent the formation of an overhang at the position of the step, whereat it would cause progressive restriction of the trench throat and void formation.

    摘要翻译： 一种多步骤HDP沉积和溅射方法，用于无缝填充具有阶梯形横截面轮廓的高纵横比沟槽。 该方法特别适用于填充形成在包括硅第一层，氧化物第二层和氮化物第三层的三层分层衬底中的沟槽，其中氮化物层从沟槽开口的边缘被拉回并形成一个台阶。 该方法允许这种沟槽的无空隙填充，而不会使该过程中的氮化物层老化。 简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比沉积，并且具有低偏压能力以在上表面形成具有突出端的层 沟。 该沉积如果随后是溅射工艺以在该突出端形成扩大的开口。 发现这种方法可以防止在台阶位置形成突出端，从而导致沟槽喉部和空隙形成的逐渐限制。

    Process of planarizing crown capacitor for integrated circuit
    9.
    发明授权
    Process of planarizing crown capacitor for integrated circuit 有权
    平面化集成电路的冠电容器的过程

    公开(公告)号：US06177307B1

    公开(公告)日：2001-01-23

    申请号：US09392158

    申请日：1999-09-08

    申请人： Yeur-Luen Tu ,  Yuan-Hung Liu

    发明人： Yeur-Luen Tu ,  Yuan-Hung Liu

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10888 ,  H01L28/87

    摘要： A method for fabricating an integrated circuit having a cell area and a peripheral circuit area in a semiconductor substrate is disclosed. First, a memory device and a transistor are formed within the cell area and the peripheral circuit area, respectively, wherein the memory device has a doped region formed in the semiconductor substrate. Then, a first insulating layer is formed to overlie the cell area and the peripheral circuit area, and thereafter patterned to be a trench over the doped region and a recess in the peripheral circuit area. Next, the first insulating layer is patterned through the trench to form a contact window, and a landing plug is filled into the contact window in contact with the doped region. Subsequently, a second insulating layer and a third insulating layer are sequentially formed to overlie the cell area and the peripheral circuit area, and then patterned to form an opening over the doped region. Next, a first conductive layer is formed on the bottom and sidewall of the opening in contact with the landing plug. Then, the third insulating layer in the cell area is removed by a planarization process, and the second insulating layer in the cell area is thereafter removed. Finally, a dielectric layer and a second conductive layer are sequentially formed over the first conductive layer.

    摘要翻译： 公开了一种在半导体衬底中制造具有单元区域和外围电路区域的集成电路的方法。 首先，存储器件和晶体管分别形成在单元区域和外围电路区域中，其中存储器件具有形成在半导体衬底中的掺杂区域。 然后，形成第一绝缘层以覆盖电池区域和外围电路区域，然后将图案化为掺杂区域上的沟槽和外围电路区域中的凹部。 接下来，通过沟槽图案化第一绝缘层以形成接触窗，并且将着陆塞填充到与掺杂区接触的接触窗中。 随后，顺序地形成第二绝缘层和第三绝缘层，以覆盖电池区域和外围电路区域，然后构图以在掺杂区域上形成开口。 接下来，第一导电层形成在与着陆塞接触的开口的底部和侧壁上。 然后，通过平坦化处理去除单元区域中的第三绝缘层，然后除去单元区域中的第二绝缘层。 最后，在第一导电层上依次形成电介质层和第二导电层。

    Magnetic memory cells and manufacturing methods
    10.
    发明授权
    Magnetic memory cells and manufacturing methods 有权
    磁记忆体和制造方法

    公开(公告)号：US07554145B2

    公开(公告)日：2009-06-30

    申请号：US11610760

    申请日：2006-12-14

    申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L29/76

    CPC分类号： H01L43/12 ,  H01L27/228

    摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

    摘要翻译： 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。