公开(公告)号：US07161821B2

公开(公告)日：2007-01-09

申请号：US10910979

申请日：2004-08-03

申请人： Chris G. Martin ,  Brent Keeth ,  Brian Johnson ,  Walter L. Moden

发明人： Chris G. Martin ,  Brent Keeth ,  Brian Johnson ,  Walter L. Moden

IPC分类号： G11C5/06

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

公开(公告)号：US06876562B2

公开(公告)日：2005-04-05

申请号：US10273869

申请日：2002-10-17

申请人： Chris G. Martin ,  Brent Keeth ,  Brian Johnson ,  Walter L. Moden

发明人： Chris G. Martin ,  Brent Keeth ,  Brian Johnson ,  Walter L. Moden

IPC分类号： G11C5/00 ,  H05K1/18 ,  G11C5/06

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

公开(公告)号：US20120246434A1

公开(公告)日：2012-09-27

申请号：US13489246

申请日：2012-06-05

申请人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

发明人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

IPC分类号： G06F12/00

CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

公开(公告)号：US07549033B2

公开(公告)日：2009-06-16

申请号：US11495418

申请日：2006-07-28

申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

公开(公告)号：US20090248970A1

公开(公告)日：2009-10-01

申请号：US12478270

申请日：2009-06-04

申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G06F12/06 ,  G06F12/04

CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

公开(公告)号：US07299329B2

公开(公告)日：2007-11-20

申请号：US10767555

申请日：2004-01-29

申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G06F12/00

CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

公开(公告)号：US5870347A

公开(公告)日：1999-02-09

申请号：US814500

申请日：1997-03-11

申请人： Brent Keeth ,  Troy A. Manning

发明人： Brent Keeth ,  Troy A. Manning

IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C7/1006

摘要： A multi-bank memory includes memory cells arranged in individually selectable banks that share column select signals. The memory cells are addressed by a row decoder that activates word lines to couple data onto digit lines. The digit lines are coupled to input/output lines through first and second series-connected switches. The first switches are input/output switches that are controlled by column select signals that are shared between multiple banks. The second switches are bank select switches that are controlled by a bank decoder, for coupling only one of the banks to input/output lines and isolating the other banks from input/output lines. The invention reduces timing requirements between operations in different banks, and allows concurrent operations in different banks, thereby increasing the speed at which the memory operates.

公开(公告)号：US09324391B2

公开(公告)日：2016-04-26

申请号：US12478270

申请日：2009-06-04

申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G06F12/02 ,  G11C7/10 ,  G06F13/16

CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

公开(公告)号：US06662304B2

公开(公告)日：2003-12-09

申请号：US10046944

申请日：2002-01-14

申请人： Brent Keeth ,  Terry R. Lee ,  Kevin Ryan ,  Troy A. Manning

发明人： Brent Keeth ,  Terry R. Lee ,  Kevin Ryan ,  Troy A. Manning

IPC分类号： G06F112

CPC分类号： G06F5/06 ,  G06F2205/102

摘要： A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches in the packetized memory device. A clock generator circuit generates a plurality of internal clock signals responsive to the external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal. A plurality of selection circuits are coupled to the clock generator circuit and each has an output coupled to a clock terminal of an associated latch. Each selection circuit applies one of the internal clock signals to clock the associated latch in response to a phase command signal. An evaluation circuit receives digital signals sequentially stored in a selected one of the latches and generates a results signal indicating whether each of the digital signals has an expected value. A control circuit sequentially selects the latches and operates for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch and store respective results signals sequentially received from the evaluation circuit for each phase command signal. The control circuit generates a final phase command signal from the stored results signals and applies each final phase command signal to the corresponding selection circuit Each of the final phase command signals adjusts the phase of clock signal applied to the associated latch relative to the digital signal applied to the latch so that the digital signal is successfully captured responsive to the clock signal.

公开(公告)号：US06412052B2

公开(公告)日：2002-06-25

申请号：US09748955

申请日：2000-12-26

申请人： Brent Keeth ,  Troy A. Manning

发明人： Brent Keeth ,  Troy A. Manning

IPC分类号： G06F1200

CPC分类号： G11C7/1072 ,  G11C7/20

摘要： A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal. In another embodiment, the initialization flag detection system includes a plurality of latches receiving the flag signals at their data inputs. The latches are clocked by respective strobe signals corresponding to the command clock signal, but having phases that differ from each other. The outputs of the latches are applied to a logic circuit, such as a NAND gate. Finally, in another embodiment of the invention, the bits of the command packet are sampled along with the flag signal and compared to the samples of the flag signal to detect when a command packet having a predetermined pattern does not correspond to a flag signal having a predetermined pattern.

摘要翻译： 用于检测初始化标志信号并将其与具有初始化标志信号的持续时间的一半的正常标志信号区分开的系统。 初始化标志检测系统可以包括在计算机系统中使用的分组化DRAM的命令缓冲器中。 在一个实施例中，初始化标志检测系统包括在它们各自的数据输入端接收标志信号的一对移位寄存器。 一个移位寄存器由对应于外部施加到命令时钟信号的信号计时，而另一个移位寄存器由正交时钟信号计时。 移位寄存器一起存储长于正常标志信号的持续时间的持续时间的采样数量。 当存储在移位寄存器中的所有采样都对应于标志信号的逻辑电平时，移位寄存器的输出被施加到逻辑电路，例如与非门，其产生初始化信号。 在另一个实施例中，初始化标志检测系统包括在其数据输入端接收标志信号的多个锁存器。 锁存器由对应于命令时钟信号的相应选通信号计时，但具有彼此不同的相位。 锁存器的输出被施加到诸如NAND门的逻辑电路。 最后，在本发明的另一个实施例中，命令分组的比特与标志信号一起被采样，并与标志信号的样本进行比较，以检测何时具有预定模式的命令分组不对应于具有 预定模式。