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58 条记录 (耗时 0.022 秒)

    Method and structure for creating ultra low resistance damascene copper wiring
    41.
    发明授权
    Method and structure for creating ultra low resistance damascene copper wiring 有权
    制造超低电阻大马士革铜线的方法和结构

    公开(公告)号：US07196420B1

    公开(公告)日：2007-03-27

    申请号：US11259965

    申请日：2005-10-26

    申请人： Peter A. Burke ,  Hongqiang Lu ,  Sey-Shing Sun

    发明人： Peter A. Burke ,  Hongqiang Lu ,  Sey-Shing Sun

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76841

    摘要： A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

    摘要翻译： 通过在通孔和沟槽结构的侧壁上形成诸如SiC或SiOC的薄介电膜来形成低电阻铜镶嵌互连结构，起到铜扩散阻挡层的作用。 通过各向异性蚀刻去除在沟槽结构的底部形成的电介质铜扩散屏障，以露出图案化的金属区域。 因此，残余电介质在结构的侧壁上形成电介质扩散阻挡膜，并与随后在沟槽中形成的金属扩散阻挡层耦合，形成铜扩散阻挡层，以保护大块电介质免受铜泄漏。

    Electroluminescent phosphor thin films
    44.
    发明授权
    Electroluminescent phosphor thin films 有权
    电致发光荧光粉薄膜

    公开(公告)号：US06242858B1

    公开(公告)日：2001-06-05

    申请号：US09153266

    申请日：1998-09-14

    申请人： Sey-Shing Sun

    发明人： Sey-Shing Sun

    IPC分类号： H01J162

    CPC分类号： H05B33/14 ,  C09K11/586 ,  C09K11/625

    摘要： A light emitting phosphor having improved luminance is incorporated into an ACTFEL device which includes a phosphor layer having the formula MIIS:Cu,Ag where MII is taken from the group calcium, strontium, barium and magnesium, S is sulfur, Cu is copper, and Ag is silver.

    摘要翻译： 具有改善的亮度的发光荧光体被并入ACTFEL装置，其包括具有式MIIS：Cu，Ag的荧光体层，其中MII取自钙，锶，钡和镁，S为硫，Cu为铜， 银是银。

    Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow
    48.
    发明授权
    Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
    门边缘衬垫的应用以保持栅极长度CD在替代栅极晶体管流中

    公开(公告)号：US08384165B2

    公开(公告)日：2013-02-26

    申请号：US12140773

    申请日：2008-06-17

    申请人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    发明人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    IPC分类号： H01L29/49 ,  H01L29/51

    CPC分类号： H01L29/49 ,  G02B6/3897 ,  G02B6/445 ,  H01L29/51 ,  H02G15/117

    摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

    摘要翻译： 保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。 衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。 该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于 模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

    Bi-axial texturing of high-K dielectric films to reduce leakage currents
    49.
    发明授权
    Bi-axial texturing of high-K dielectric films to reduce leakage currents 有权
    高K电介质膜的双轴纹理化以减少漏电流

    公开(公告)号：US07956401B2

    公开(公告)日：2011-06-07

    申请号：US12574479

    申请日：2009-10-06

    申请人： Wai Lo ,  Sey-Shing Sun ,  Wilbur Catabay

    发明人： Wai Lo ,  Sey-Shing Sun ,  Wilbur Catabay

    IPC分类号： H01L21/336

    CPC分类号： H01L29/51 ,  C23C14/226 ,  C23C14/3442 ,  C23C14/46 ,  C23C16/486 ,  H01L21/02189 ,  H01L21/02266 ,  H01L21/28194 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645

    摘要： The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain boundaries. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The result is a dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

    摘要翻译： 本发明涉及制造在膜的晶界处具有高度晶体取向度的高K电介质膜的方法。 所公开的方法包括提供衬底，然后沉积辅助有离子束的高K电介质材料，以便优先形成具有选定结晶取向的晶格。 所得介电膜在晶界处具有高度的结晶取向。 另一公开的方法包括提供衬底，然后将材料成角度地沉积到衬底上，以帮助优先形成具有选定结晶取向的晶格。 结果是在膜的晶界处具有高度结晶取向的电介质膜。