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    Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow
    1.
    发明授权
    Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
    门边缘衬垫的应用以保持栅极长度CD在替代栅极晶体管流中

    公开(公告)号：US07405116B2

    公开(公告)日：2008-07-29

    申请号：US10916322

    申请日：2004-08-11

    申请人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    发明人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    IPC分类号： H01L21/338

    CPC分类号： H01L29/6656 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

    摘要翻译： 保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。 衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。 该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于 模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

    Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow
    2.
    发明授权
    Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
    门边缘衬垫的应用以保持栅极长度CD在替代栅极晶体管流中

    公开(公告)号：US08384165B2

    公开(公告)日：2013-02-26

    申请号：US12140773

    申请日：2008-06-17

    申请人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    发明人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    IPC分类号： H01L29/49 ,  H01L29/51

    CPC分类号： H01L29/49 ,  G02B6/3897 ,  G02B6/445 ,  H01L29/51 ,  H02G15/117

    摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

    摘要翻译： 保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。 衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。 该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于 模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

    APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW
    3.
    发明申请
    APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW 有权
    门盖边缘应用于更换门盖晶体管流程中的门长度CD

    公开(公告)号：US20080308882A1

    公开(公告)日：2008-12-18

    申请号：US12140773

    申请日：2008-06-17

    申请人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    发明人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    IPC分类号： H01L29/00

    CPC分类号： H01L29/49 ,  G02B6/3897 ,  G02B6/445 ,  H01L29/51 ,  H02G15/117

    摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

    摘要翻译： 保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。 衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。 该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于 模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

    Self-aligned cell integration scheme
    9.
    发明授权
    Self-aligned cell integration scheme 失效
    自对准单元集成方案

    公开(公告)号：US07915122B2

    公开(公告)日：2011-03-29

    申请号：US11312849

    申请日：2005-12-20

    申请人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    发明人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    IPC分类号： H01L21/336

    CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

    摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

    摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。

    Self-aligned cell integration scheme
    10.
    发明申请
    Self-aligned cell integration scheme 失效
    自对准单元集成方案

    公开(公告)号：US20060281256A1

    公开(公告)日：2006-12-14

    申请号：US11312849

    申请日：2005-12-20

    申请人： Richard Carter ,  Hemanshu Bhatt ,  Shiqun Gu ,  Peter Burke ,  James Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    发明人： Richard Carter ,  Hemanshu Bhatt ,  Shiqun Gu ,  Peter Burke ,  James Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    IPC分类号： H01L21/336

    CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

    摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

    摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。