公开(公告)号：US5858835A

公开(公告)日：1999-01-12

申请号：US996193

申请日：1997-12-22

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L28/84

Abstract: A method for fabricating a capacitor over a semiconductor substrate is disclosed. The method includes the steps of: forming an insulating layer over the semiconductor substrate; forming a contact opening through the insulating layer to expose a portion of the semiconductor substrate; forming a first polysilicon layer over the insulating layer and filling in the contact opening to electrically contact the semiconductor substrate; patterning the first polysilicon layer to the insulating layer surface, thereby forming a trench for defining a capacitor region; forming a thin polysilicon layer with a rugged surface over the first polysilicon layer and the insulating layer; forming a mask layer over the thin polysilicon layer, wherein the mask layer has a smaller thickness in the trench bottom than in other regions; removing the mask layer in the trench bottom through an anisotropical etch step; removing the uncovered portions of the thin polysilicon layer to expose the insulating layer surface; removing the mask layer, thereby forming a storage electrode consisting of the thin polysilicon layer and the first polysilicon layer; forming a dielectric layer over the storage electrode and the exposed insulating layer; and forming a second polysilicon layer over the dielectric layer.

Abstract translation: 公开了一种在半导体衬底上制造电容器的方法。 该方法包括以下步骤：在半导体衬底上形成绝缘层; 形成通过所述绝缘层的接触开口以暴露所述半导体衬底的一部分; 在所述绝缘层上形成第一多晶硅层，并填充所述接触开口以电接触所述半导体衬底; 将第一多晶硅层图案化成绝缘层表面，从而形成用于限定电容器区域的沟槽; 在所述第一多晶硅层和所述绝缘层上形成具有凹凸表面的薄多晶硅层; 在所述薄多晶硅层上形成掩模层，其中所述掩模层在所述沟槽底部具有比在其它区域更小的厚度; 通过各向异性热蚀刻步骤去除沟槽底部中的掩模层; 去除所述薄多晶硅层的未覆盖部分以暴露所述绝缘层表面; 去除掩模层，从而形成由薄多晶硅层和第一多晶硅层组成的存储电极; 在所述存储电极和所述暴露的绝缘层上形成介电层; 以及在所述电介质层上形成第二多晶硅层。

公开(公告)号：US07135731B2

公开(公告)日：2006-11-14

申请号：US10707396

申请日：2003-12-10

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10876 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

Abstract translation: 垂直DRAM及其制造方法。 垂直DRAM在衬底上具有多个存储单元，并且每个存储单元在深沟槽中具有沟槽电容器，垂直晶体管和源极隔离氧化物层。 本发明的主要优点是在深沟槽的侧壁周围形成环形源极扩散和垂直晶体管的环形漏极扩散。 结果，当晶体管的栅极导通时，提供环形栅极沟道。 因此，本发明的栅极通道的宽度增加。

公开(公告)号：US06995061B2

公开(公告)日：2006-02-07

申请号：US10779607

申请日：2004-02-18

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

公开(公告)号：US20050156233A1

公开(公告)日：2005-07-21

申请号：US11076499

申请日：2005-03-09

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

Abstract translation: 堆叠式栅极闪存器件及其制造方法。 层叠栅极闪存器件的单元被布置在衬底内的单元沟槽中，以实现存储单元的更高集成度。

公开(公告)号：US5872041A

公开(公告)日：1999-02-16

申请号：US933008

申请日：1997-09-18

Applicant: Ta-Yuan Lee ,  Chi-Hui Lin

Inventor： Ta-Yuan Lee ,  Chi-Hui Lin

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: A method for fabricating electrodes of a capacitor over a semiconductor substrate is disclosed. The method includes the steps of: forming a base insulating layer over the semiconductor substrate; forming a stacked layer, including an insulating layer and a mask layer, over the base insulating layer; defining the stacked layer to form an opening to the base insulating layer; forming a first conducting layer over the stacked layer; forming a spacer on the sidewall of the first conducting layer in the opening; etching the bottom of the opening by using the mask layer and the spacer as a mask to expose a portion of the semiconductor substrate; forming a second conducting layer in the opening to electrically connect the exposed semiconductor substrate; and removing the spacer to leave the first and the second conducting layers as a capacitor electrode.

Abstract translation: 公开了一种在半导体衬底上制造电容器的电极的方法。 该方法包括以下步骤：在半导体衬底上形成基极绝缘层; 在所述基底绝缘层上形成包括绝缘层和掩模层的层叠层; 限定所述堆叠层以形成到所述基底绝缘层的开口; 在堆叠层上形成第一导电层; 在所述开口中的所述第一导电层的侧壁上形成间隔物; 通过使用掩模层和间隔物作为掩模蚀刻开口的底部以暴露半导体衬底的一部分; 在所述开口中形成第二导电层以电连接所暴露的半导体衬底; 并且移除间隔物以将第一和第二导电层留作电容器电极。