LOW RESISTANCE ULTRAVIOLET LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME
    41.
    发明申请
    LOW RESISTANCE ULTRAVIOLET LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME 有权
    低电阻超紫外线发光装置及其制造方法

    公开(公告)号:US20110012089A1

    公开(公告)日:2011-01-20

    申请号:US12934650

    申请日:2009-03-27

    IPC分类号: H01L33/04 H01L33/30

    摘要: A low resistance light emitting device with an ultraviolet light-emitting structure having a first layer with a first conductivity, a second layer with a second conductivity; and a light emitting quantum well region between the first layer and second layer. A first electrical contact is in electrical connection with the first layer and a second electrical contact is in electrical connection with the second layer. A template serves as a platform for the light-emitting structure. The ultraviolet light-emitting structure has a first layer having a first portion and a second portion of AlXInYGa(1-X-Y)N with an amount of elemental indium, the first portion surface being treated with silicon and indium containing precursor sources, and a second layer. When an electrical potential is applied to the first layer and the second layer the device emits ultraviolet light.

    摘要翻译: 一种具有紫外发光结构的低电阻发光器件,具有具有第一导电性的第一层,具有第二导电性的第二层; 以及在第一层和第二层之间的发光量子阱区。 第一电触头与第一层电连接,第二电接触与第二层电连接。 模板作为发光结构的平台。 紫外发光结构具有第一层,其具有一定量的元素铟的AlXInYGa(1-XY)N的第一部分和第二部分,第一部分表面用含有铟和铟的前体源进行处理,第二层由第二层 层。 当电势施加到第一层和第二层时,该装置发射紫外光。

    Link layer device with non-linear polling of multiple physical layer device ports
    42.
    发明申请
    Link layer device with non-linear polling of multiple physical layer device ports 有权
    具有多个物理层设备端口的非线性轮询的链路层设备

    公开(公告)号:US20050169298A1

    公开(公告)日:2005-08-04

    申请号:US10768764

    申请日:2004-01-30

    IPC分类号: H04L12/24 H04L12/403

    CPC分类号: H04L41/00

    摘要: In a communication system comprising a link layer device connectable to one or more physical layer devices, at least a given one of a plurality of ports of the one or more physical layer devices is designated as a port for which status information is to be requested by the link layer device on a more frequent basis than such information is to be requested for one or more other ports of the plurality of ports. The ports are then polled by the link layer device in accordance with a non-linear polling sequence such that the at least one designated port is polled more frequently than the one or more other ports. The designated port may comprise a port to which the link layer device transmits data in conjunction with a current data transfer. The non-linear polling sequence may thus be altered dynamically based on particular data transfers that are occurring between a link layer device and a physical layer device in a communication system.

    摘要翻译: 在包括可连接到一个或多个物理层设备的链路层设备的通信系统中,一个或多个物理层设备的多个端口中的至少一个给定的一个被指定为要由其请求状态信息的端口 对于多个端口中的一个或多个其他端口,要求比这种信息更频繁的链路层设备。 然后根据非线性轮询序列由链路层设备轮询端口,使得至少一个指定端口比一个或多个其他端口更频繁地轮询。 指定端口可以包括链路层设备结合当前数据传输发送数据的端口。 因此,可以基于在通信系统中的链路层设备和物理层设备之间发生的特定数据传输来动态地改变非线性轮询序列。

    Link layer device with configurable address pin allocation
    43.
    发明申请
    Link layer device with configurable address pin allocation 有权
    链路层设备具有可配置的地址引脚分配

    公开(公告)号:US20050138259A1

    公开(公告)日:2005-06-23

    申请号:US10744567

    申请日:2003-12-23

    IPC分类号: G06F13/14 G06F13/38

    CPC分类号: G06F13/385

    摘要: Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the link layer device associated therewith, the interface bus being configurable to carry a composite address signal having a plurality of portions each associated with one of the address pins of the interface bus. The interface blocks of the link layer device are controlled such that each of at least a subset of the interface blocks utilizes only particular ones of the address pins that are controllably allocated to the associated sub-bus in accordance with configuration information stored in the link layer device. The composite address signal is generated as a combination of address outputs of the interface blocks.

    摘要翻译: 公开了用于将接口总线的地址引脚灵活分配给接口总线的特定子总线的技术。 接口总线在通信系统中的至少一个物理层设备和链路层设备之间。 每个子总线具有与其相关联的链路层设备的接口块,该接口总线可配置为承载具有多个部分的复合地址信号,每个部分与接口总线的一个地址引脚相关联。 控制链路层设备的接口块,使得接口块的至少一个子集中的每一个仅使用根据存储在链路层中的配置信息可控地分配给相关联的子总线的特定地址引脚 设备。 复合地址信号作为接口块的地址输出的组合生成。

    Distributed system architecture using event stream processing
    44.
    发明授权
    Distributed system architecture using event stream processing 有权
    使用事件流处理的分布式系统架构

    公开(公告)号:US09548910B2

    公开(公告)日:2017-01-17

    申请号:US14283509

    申请日:2014-05-21

    申请人: Asif Khan

    发明人: Asif Khan

    IPC分类号: H04L12/26 H04L29/08 H04L29/06

    摘要: A system and method for performing event stream processing is described. A plurality of event streams are received from a plurality of input adapters, at least a first input adapter of the plurality of input adapters being located on a separate and distinct virtual machine than a second input adapter of the plurality of input adapters. Event stream data from the first input adapter and event stream data from the second input adapter are transformed into data of a single data type. The transformed data is stored in an in-memory database. Then real-time analysis is performed on the transformed data by accessing windows of the transformed data from the in-memory database based on rules defined in the event stream processing engine.

    摘要翻译: 描述用于执行事件流处理的系统和方法。 从多个输入适配器接收多个事件流,多个输入适配器中的至少第一输入适配器位于与多个输入适配器中的第二输入适配器分开且不同的虚拟机上。 来自第一输入适配器的事件流数据和来自第二输入适配器的事件流数据被转换成单个数据类型的数据。 变换后的数据存储在内存数据库中。 然后,根据在事件流处理引擎中定义的规则,通过从存储器内数据库访问转换数据的窗口,对变换后的数据执行实时分析。

    Selectively area regrown III-nitride high electron mobility transistor
    45.
    发明授权
    Selectively area regrown III-nitride high electron mobility transistor 有权
    选择性区域再生长的III族氮化物高电子迁移率晶体管

    公开(公告)号:US08796097B2

    公开(公告)日:2014-08-05

    申请号:US13870558

    申请日:2013-04-25

    摘要: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.

    摘要翻译: 提供了形成HEMT器件的方法。 该方法包括在多个薄膜层上形成超薄势垒层。 在超薄阻挡层的一部分上形成电介质薄膜层以留下超薄势垒层的暴露区域。 在超薄阻挡层的暴露区域上形成SAG S-D薄膜层,同时露出电介质薄膜层。 然后去除电介质薄膜层以暴露下面的超薄势垒层。 用氟处理下面的超薄阻挡层以形成处理区域。 在SAG S-D薄膜层上添加源极和漏极,并且在用氟处理的超薄势垒层上沉积电介质涂层,使得介电涂层位于源极和漏极之间。

    DIGITAL OXIDE DEPOSITION OF SIO2 LAYERS ON WAFERS
    46.
    发明申请
    DIGITAL OXIDE DEPOSITION OF SIO2 LAYERS ON WAFERS 有权
    SIO2层的数字氧化硅沉积在水面上

    公开(公告)号:US20130017689A1

    公开(公告)日:2013-01-17

    申请号:US11800712

    申请日:2007-05-07

    IPC分类号: H01L21/316

    摘要: Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about 65° C. and about 350° C. The heated substrate is exposed to a silicon source that is substantially free from an oxidizing agent. The silicon on the surface is then oxidized with an oxygen source that is substantially free from a silicon source. As a result of oxidizing the silicon, a silicon oxide layer forms on the surface of the substrate. Alternatively, or in additionally, a nitrogen source can be provided to produce silicon nitride on the surface of the substrate.

    摘要翻译: 通常公开了新的二氧化硅和氮化硅沉积方法。 在一个实施例中,该方法包括在温度在约65℃至约350℃之间的衬底的表面上沉积硅。将加热的衬底暴露于基本上不含氧化剂的硅源。 然后用基本上不含硅源的氧源氧化表面上的硅。 作为氧化硅的结果,在衬底的表面上形成氧化硅层。 或者,或另外,可以提供氮源以在衬底的表面上产生氮化硅。

    Vertical deep ultraviolet light emitting diodes
    47.
    发明授权
    Vertical deep ultraviolet light emitting diodes 有权
    垂直深紫外发光二极管

    公开(公告)号:US08242484B2

    公开(公告)日:2012-08-14

    申请号:US12445945

    申请日:2007-10-17

    申请人: Asif Khan

    发明人: Asif Khan

    IPC分类号: H01L33/06

    摘要: The invention is a vertical geometry light emitting diode capable of emitting light in the electromagnetic spectrum having a substrate, a lift-off layer, a strain relieved superlattice layer, a first doped layer, a multilayer quantum wells comprising alternating layers quantum wells and barrier layers, a second doped layer, a third doped layer and a metallic contact that is in a vertical geometry orientation. The different layers consist of a compound with the formula AlxlnyGa(1-x-y)N, wherein x is more than 0 and less than or equal to 1, y is from 0 to 1 and x+y is greater than 0 and less than or equal to 1. The barrier layer on each surface of the quantum well has a band gap larger than a quantum well bandgap. The first and second doped layers have different conductivities. The contact layer has a different conductivity than the third doped layer.

    摘要翻译: 本发明是能够在电磁光谱中发射光的垂直几何形状的发光二极管,其具有衬底,剥离层,应变消除的超晶格层,第一掺杂层,包含交替层量子阱和势垒层的多层量子阱 ,第二掺杂层,第三掺杂层和处于垂直几何取向的金属接触。 不同的层由具有式AlxlnyGa(1-xy)N的化合物组成,其中x大于0且小于或等于1,y为0至1,x + y大于0且小于或等于 等于1.量子阱的每个表面上的阻挡层具有大于量子阱带隙的带隙。 第一和第二掺杂层具有不同的电导率。 接触层具有与第三掺杂层不同的导电性。

    Virtualization bridge device
    48.
    发明授权
    Virtualization bridge device 有权
    虚拟化桥设备

    公开(公告)号:US07979592B1

    公开(公告)日:2011-07-12

    申请号:US12028801

    申请日:2008-02-09

    IPC分类号: G06F3/00

    CPC分类号: G06F13/404

    摘要: A computer system includes a shared I/O device including functions providing access to device local memory space, and a plurality of roots coupled to the shared I/O device via a switch fabric. A first root assigns a first address in a first root memory space to a first function. A second root assigns a second address in a second root memory space to a second function. The switch fabric maps the first root memory space to a first portion of device local memory space and the second root memory space to a second portion of device local memory space. Subsequently, the switch receives a data transaction request from the first root targeted to the first address, translates the first address to a corresponding location in the first portion of the device local memory space based on the mapping, and routes the data transaction request to the I/O device.

    摘要翻译: 计算机系统包括共享I / O设备,其包括提供对设备本地存储器空间的访问的功能,以及经由交换结构耦合到共享I / O设备的多个根。 第一根将第一根存储器空间中的第一地址分配给第一功能。 第二根将第二根存储器空间中的第二地址分配给第二功能。 交换结构将第一根存储器空间映射到设备本地存储器空间的第一部分,将第二根存储器空间映射到设备本地存储器空间的第二部分。 随后,交换机从第一根目标地址到第一地址接收数据事务请求,基于映射将第一地址转换到设备本地存储器空间的第一部分中的对应位置,并将数据事务请求路由到 I / O设备。

    MULTILAYER BARRIER III-NITRIDE TRANSISTOR FOR HIGH VOLTAGE ELECTRONICS
    49.
    发明申请
    MULTILAYER BARRIER III-NITRIDE TRANSISTOR FOR HIGH VOLTAGE ELECTRONICS 有权
    用于高压电子的多层氮化物III-NITRIDE晶体管

    公开(公告)号:US20110108887A1

    公开(公告)日:2011-05-12

    申请号:US12941332

    申请日:2010-11-08

    IPC分类号: H01L29/778 H01L21/335

    摘要: An improved high breakdown voltage semiconductor device and method for manufacturing is provided. The device has a substrate and a AlaGa1-aN layer on the substrate wherein 0.1≦a≦1.00. A GaN layer is on the AlaGa1-aN layer. An In1-bGabN/GaN channel layer is on the GaN layer wherein 0.1≦b≦1.00. A AlcIndGa1-c-dN spacer layer is on the In1-bGabN/GaN layer wherein 0.1≦c≦1.00 and 0.0≦d≦0.99. A AleIn1-eN nested superlattice barrier layer is on the AlcIndGa1-c-dN spacer layer wherein 0.10≦e≦0.99. A AlfIngGa1-f-gN leakage suppression layer is on the AleIn1-eN barrier layer wherein 0.1≦f≦0.99 and 0.1≦g≦0.99 wherein the leakage suppression layer decreases leakage current and increases breakdown voltage during high voltage operation. A superstructure, preferably with metallic electrodes, is on the AlfIngGa1-f-gN leakage suppression layer.

    摘要翻译: 提供了一种改进的高击穿电压半导体器件及其制造方法。 该器件在衬底上具有衬底和AlaGa1-aN层,其中0.1< 1; a≦̸ 1.00。 Ala层在AlaGa1-aN层上。 In 1-bGabN / GaN沟道层位于GaN层上,其中0.1< 1; b≦̸ 1.00。 AlcIndGa1-c-dN间隔层位于In1-bGabN / GaN层上,其中0.1& NlE; c≦̸ 1.00和0.0& nlE; d≦̸ 0.99。 AlInInGa1-c-dN间隔层上的AleIn1-eN嵌层超晶格势垒层,其中0.10< 1Ee; e≦̸ 0.99。 AlInInGaGa1-f-gN泄漏抑制层位于AleIn1-eN阻挡层上,其中0.1≦̸ f≦̸ 0.99和0.1≦̸ g≦̸ 0.99,其中泄漏抑制层降低泄漏电流并增加高压操作期间的击穿电压。 在AlfIngGa1-f-gN泄漏抑制层上,优选具有金属电极的上层结构。

    MICRO-PIXEL ULTRAVIOLET LIGHT EMITTING DIODE
    50.
    发明申请
    MICRO-PIXEL ULTRAVIOLET LIGHT EMITTING DIODE 有权
    微型超紫外线发光二极管

    公开(公告)号:US20100264401A1

    公开(公告)日:2010-10-21

    申请号:US12673476

    申请日:2008-08-13

    IPC分类号: H01L33/04 H01L33/00

    摘要: An ultra-violet light-emitting diode (LED) array, 12, and method for fabricating same with an AlInGaN multiple-quantum-well active region, 500, exhibiting stable cw-powers. The LED includes a template, 10, with an ultraviolet light-emitting array structure on it. The template includes a first buffer layer, 321, then a second buffer layer, 421, on the first preferably with a strain-relieving layer in both buffer layers. Next there is a semiconductor layer having a first type of conductivity, 500, followed by a layer providing a quantum-well region, 600, with an emission spectrum ranging from 190 nm to 369 nm. Another semiconductor layer having a second type of conductivity is applied next, 800. A first metal contact, 980, is a charge spreading layer in electrical contact with the first layer and between the array of LED's. A second contact, 990, is applied to the semiconductor layer having the second type of conductivity, to complete the LED.

    摘要翻译: 一种紫外发光二极管(LED)阵列12及其制造方法,具有稳定的cw功率的AlInGaN多量子阱有源区500。 LED包括一个具有紫外发光阵列结构的模板10。 模板包括第一缓冲层321,然后第二缓冲层421,优选地在两个缓冲层中具有应变消除层。 接下来,存在具有第一类型导电性的半导体层500,随后是提供量子阱区域的层600,发射光谱范围为190nm至369nm。 接下来施加另一种具有第二类导电性的半导体层,800.第一金属触点980是与第一层电连接并在LED阵列之间的电荷扩散层。 第二触点990被施加到具有第二类导电性的半导体层,以完成LED。