公开(公告)号：US06639868B2

公开(公告)日：2003-10-28

申请号：US10112108

申请日：2002-03-28

申请人： Kyu-Hyoun Kim ,  Dae-Hyun Chung

发明人： Kyu-Hyoun Kim ,  Dae-Hyun Chung

IPC分类号： G11C800

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C2207/107

摘要： A synchronous DRAM semiconductor device including a data latch circuit outputting input data responsive to with a plurality of control signals is provided. The synchronous DRAM semiconductor device includes a first buffer for buffering an external control signal and generating a first internal control signal. A second buffer buffers the external control signal and generating a second internal control signal. A third buffer buffers the external control signal and generates an internal clock signal. A data latch circuit receives external data sequentially synchronized with the first and second internal control signals and the internal clock signal. The synchronous DRAM semiconductor device can prevent the time margin window for outputting data from the data latch circuit.

公开(公告)号：US08659959B2

公开(公告)日：2014-02-25

申请号：US13567353

申请日：2012-08-06

申请人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

发明人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G06F11/1028 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

摘要翻译： 具有改进性能，降低功耗和增加可靠性的高级内存。 存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路 对错误控制编码电路检测接收到的命令中的错误。 另一个存储器件包括可编程序序。 另一存储器件包括快速退出自刷新模式。 另一种存储装置包括由特征装置控制的自动刷新功能。 另一存储器件包括由存储器件的特性控制的自动刷新功能。

公开(公告)号：US08432027B2

公开(公告)日：2013-04-30

申请号：US12616563

申请日：2009-11-11

申请人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

IPC分类号： H01L23/538 ,  H01L23/48

CPC分类号： H01L23/5384 ,  H01L21/822 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555

摘要： An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.

摘要翻译： 一种集成电路管芯堆叠，其包括安装在衬底上的第一集成电路管芯，所述第一管芯包括由通过所述第一管芯的导电通路组成的通孔（“PTV”），其没有连接到所述第一管芯上的任何电路; 以及第一集成电路管芯，与第一管芯相同，相对于第一管芯旋转并且安装在第一管芯上，第一管芯中的PTV将信号线从衬底通过第一管芯连接到硅通孔（“ TSV），其通过连接到第二管芯上的电子电路的第二管芯的导电通路构成; 其中TSV和PTV设置在每个相同的管芯上，使得每个相同管芯上的TSV和PTV的位置相对于另一相同管芯上的TSV和PTV旋转对称。

公开(公告)号：US20120300570A1

公开(公告)日：2012-11-29

申请号：US13567357

申请日：2012-08-06

申请人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

发明人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

IPC分类号： G11C11/402

CPC分类号： G11C7/1078 ,  G06F11/1028 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

公开(公告)号：US20120299640A1

公开(公告)日：2012-11-29

申请号：US13569267

申请日：2012-08-08

申请人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

IPC分类号： H01H37/76 ,  H01L21/50 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L23/5256 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

摘要翻译： 集成电路芯片堆叠，其具有安装在基板上的第一裸片，所述第一模具被制造成与具有多个穿通硅通孔（TSV）的第二裸片最初相同，所述第一裸片通过在第一裸片上熔化熔丝而被个性化， 先前通过熔断保险丝连接的TSV通过通孔（PTV），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。

公开(公告)号：US08315068B2

公开(公告)日：2012-11-20

申请号：US12616912

申请日：2009-11-12

申请人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： H01L23/481 ,  H01L23/5256 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

摘要翻译： 集成电路芯片堆叠，其具有安装在基板上的第一裸片，所述第一模具被制造成与具有多个穿通硅通孔（TSV）的第二裸片最初相同，所述第一裸片通过在第一裸片上熔化熔丝而被个性化， 先前通过熔断保险丝连接的TSV通过通孔（PTV），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。

公开(公告)号：US20120286431A1

公开(公告)日：2012-11-15

申请号：US13556976

申请日：2012-07-24

申请人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

IPC分类号： H01L23/522 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L25/18 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

摘要翻译： 具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（TSV）的第二管芯最初相同，所述第一管芯通过在第一管芯上打开开关来个性化， 先前通过开放式开关连接的TSV通过通孔（PTV），每个PTV实现通过第一管芯的导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过打开第二模具上的开关进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。

公开(公告)号：US08307270B2

公开(公告)日：2012-11-06

申请号：US12553400

申请日：2009-09-03

申请人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

发明人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

IPC分类号： G11C29/00

CPC分类号： G11C7/1078 ,  G06F11/1028 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

摘要翻译： 具有改进性能，降低功耗和增加可靠性的先进内存。 存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路 对错误控制编码电路检测接收到的命令中的错误。 另一个存储器件包括可编程序序。 另一存储器件包括快速退出自刷新模式。 另一种存储装置包括由特征装置控制的自动刷新功能。 另一存储器件包括由存储器件的特性控制的自动刷新功能。

公开(公告)号：US08253478B2

公开(公告)日：2012-08-28

申请号：US12325846

申请日：2008-12-01

申请人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

发明人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

IPC分类号： G05F1/10

CPC分类号： G05F1/465

摘要： An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.

摘要翻译： 提供内部电压产生电路。 半导体器件的内部电压产生电路包括：控制信号发生电路，用于根据多个数据位产生控制信号;比较器，用于将参考电压与内部电压进行比较，以在控制信号失效时产生驱动信号 ，用于当所述控制信号被激活时使所述驱动信号失活的驱动信号控制电路和用于接收外部电源电压并且响应于所述驱动信号产生所述内部电压的内部电压驱动电路。 因此，可以根据半导体器件的数据输入和/或输出位的数量将内部电压转换为参考电压电平或外部电源电压，并且即使当数据输入和/或输出位数 增加，可以提高数据访问速度。

公开(公告)号：US20110110065A1

公开(公告)日：2011-05-12

申请号：US12617273

申请日：2009-11-12

申请人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

IPC分类号： H05K1/14 ,  H01L23/538 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L25/18 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

摘要翻译： 具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（“TSV”）的第二管芯初始相同，所述第一管芯通过在第一管芯上打开开关来个性化， 将先前通过开放式开关连接的TSV转换成通过通孔（“PTV”），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过打开第二模具上的开关进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。