公开(公告)号：US6144059A

公开(公告)日：2000-11-07

申请号：US375638

申请日：1999-08-17

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01L21/02 ,  H01L27/108

CPC classification number: H01L28/84

Abstract: The present invention provides a process and a structure for increasing a capacitance of a stack capacitor. The process includes steps of: a) forming a contact hole on a silicon substrate having an oxide layer, b) forming a polysilicon contact plug of a first polysilicon layer in the contact hole; c) forming a second gibbous polysilicon layer on a surface of the contact plug, and d) forming a third polysilicon layer above the gibbous polysilicon layer and a portion of the oxide layer to form the stack capacitor, wherein the gibbous polysilicon layer increases the capacitance of the stack capacitor.

公开(公告)号：US6063548A

公开(公告)日：2000-05-16

申请号：US148565

申请日：1998-09-04

Applicant: Wen-Ting Chu ,  Chung-Cheng Wu

Inventor： Wen-Ting Chu ,  Chung-Cheng Wu

IPC: H01L21/02 ,  H01L21/8242 ,  G03C5/00

CPC classification number: H01L28/92 ,  H01L27/10852

Abstract: A method for forming stacked capacitors for DRAMs using a single photoresist mask and having bottom electrodes self-aligned to node contacts is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. A first silicon nitride (Si.sub.3 N.sub.4) hard mask layer is deposited and a second insulating layer is deposited. First openings are etched, partially into the first insulating layer, for the capacitor bottom electrodes. A second Si.sub.3 N.sub.4 layer is deposited and etched back to form sidewall spacers in the first openings. The Si.sub.3 N.sub.4 hard mask and spacers are used to etch second openings (node contacts) in the first insulating layer, self-aligned in the first openings and to the source/drain contact areas. A first polysilicon layer is deposited and etched back to form recessed polysilicon plugs in the first openings. A third Si.sub.3 N.sub.4 layer is deposited and etched back to form sidewall spacers on the plugs in the first openings and is used as a mask to etch the polysilicon to form the vertical sidewalls of the bottom electrodes self-aligned to the node contacts. The first insulating layer is recessed to expose the bottom electrodes. An interelectrode dielectric layer is formed on the bottom electrodes, and a patterned second polysilicon layer is used for the top electrodes.

Abstract translation: 实现了使用单个光致抗蚀剂掩模形成用于DRAM的堆叠电容器并且具有与节点接触自对准的底部电极的方法。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层。 沉积第一氮化硅（Si 3 N 4）硬掩模层并沉积第二绝缘层。 对于电容器底部电极，第一开口部分地被蚀刻到第一绝缘层中。 第二Si 3 N 4层被沉积并回蚀刻以在第一开口中形成侧壁间隔物。 Si 3 N 4硬掩模和间隔物用于蚀刻第一绝缘层中的第二开口（节点接触），在第一开口中和源/漏接触区域中自对准。 沉积第一多晶硅层并将其回蚀刻以在第一开口中形成凹陷的多晶硅塞。 沉积第三个Si 3 N 4层并回蚀刻以在第一开口中的插塞上形成侧壁间隔物，并且用作掩模以蚀刻多晶硅以形成与节点接触件自对准的底部电极的垂直侧壁。 第一绝缘层凹进露出底部电极。 在底部电极上形成电极间电介质层，并且将图案化的第二多晶硅层用于顶部电极。

公开(公告)号：US5436190A

公开(公告)日：1995-07-25

申请号：US344007

申请日：1994-11-23

Applicant: Ming-Tzong Yang ,  Chung-Cheng Wu

Inventor： Ming-Tzong Yang ,  Chung-Cheng Wu

IPC: H01L21/763 ,  H01L21/76

CPC classification number: H01L21/763

Abstract: A method for fabricating a very narrow electrical isolation trench in a semiconductor substrate for isolating the individual field effect transistors (FETs) is achieved. This method eliminates the oxide encroachment into the device area associated with LOCOS techniques, thereby increasing device density. The method involves etching trenches, less than one half micrometer in width in the silicon substrate and forming sidewall spacer in the trench. The trench is filled with doped polysilicon and planarized, forming a trench which is planar with the device region. These isolation trenches are made in both N and P-wells for fabricating CMOS circuits having ULSI densities.

Abstract translation: 实现了用于在用于隔离各个场效应晶体管（FET）的半导体衬底中制造非常窄的电隔离沟槽的方法。 该方法消除了与LOCOS技术相关的器件区域的氧化物侵蚀，从而增加器件密度。 该方法包括蚀刻在硅衬底中宽度小于半微米的沟槽，并在沟槽中形成侧壁间隔物。 沟槽填充有掺杂的多晶硅并且被平坦化，形成与器件区域平坦的沟槽。 这些隔离沟槽在N阱和P阱中制造，用于制造具有ULSI密度的CMOS电路。

公开(公告)号：US08278179B2

公开(公告)日：2012-10-02

申请号：US12720476

申请日：2010-03-09

Applicant: Da-Wen Lin ,  Che-Min Chu ,  Tsung-Hung Li ,  Chih-Hung Tseng ,  Yen-Chun Lin ,  Chung-Cheng Wu

Inventor： Da-Wen Lin ,  Che-Min Chu ,  Tsung-Hung Li ,  Chih-Hung Tseng ,  Yen-Chun Lin ,  Chung-Cheng Wu

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/823821

Abstract: A method of forming a semiconductor structure includes providing a substrate including a fin at a surface of the substrate, and forming a fin field-effect transistor (FinFET), which further includes forming a gate stack on the fin; forming a thin spacer on a sidewall of the gate stack; and epitaxially growing a epitaxy region starting from the fin. After the step of epitaxially growing the epitaxy region, a main spacer is formed on an outer edge of the thin spacer. After the step of forming the main spacer, a deep source/drain implantation is performed to form a deep source/drain region for the FinFET.

Abstract translation: 一种形成半导体结构的方法包括在衬底的表面提供包括鳍的衬底，以及形成鳍状场效应晶体管（FinFET），其还包括在鳍上形成栅叠层; 在所述栅极堆叠的侧壁上形成薄的间隔物; 并从翅片开始外延生长外延区域。 在外延生长外延区域的步骤之后，在间隔物的外边缘上形成主间隔物。 在形成主间隔物的步骤之后，进行深源极/漏极注入以形成用于FinFET的深源极/漏极区域。

公开(公告)号：US20110223736A1

公开(公告)日：2011-09-15

申请号：US12720476

申请日：2010-03-09

Applicant: Da-Wen Lin ,  Che-Min Chu ,  Tsung-Hung Li ,  Chih-Hung Tseng ,  Yen-Chun Lin ,  Chung-Cheng Wu

Inventor： Da-Wen Lin ,  Che-Min Chu ,  Tsung-Hung Li ,  Chih-Hung Tseng ,  Yen-Chun Lin ,  Chung-Cheng Wu

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/823821

Abstract: A method of forming a semiconductor structure includes providing a substrate including a fin at a surface of the substrate, and forming a fin field-effect transistor (FinFET), which further includes forming a gate stack on the fin; forming a thin spacer on a sidewall of the gate stack; and epitaxially growing a epitaxy region starting from the fin. After the step of epitaxially growing the epitaxy region, a main spacer is formed on an outer edge of the thin spacer. After the step of forming the main spacer, a deep source/drain implantation is performed to form a deep source/drain region for the FinFET.

Abstract translation: 一种形成半导体结构的方法包括在衬底的表面提供包括鳍的衬底，以及形成鳍状场效应晶体管（FinFET），其还包括在鳍上形成栅叠层; 在所述栅极堆叠的侧壁上形成薄的间隔物; 并从翅片开始外延生长外延区域。 在外延生长外延区域的步骤之后，在间隔物的外边缘上形成主间隔物。 在形成主间隔物的步骤之后，进行深源极/漏极注入以形成用于FinFET的深源极/漏极区域。

公开(公告)号：US20110147765A1

公开(公告)日：2011-06-23

申请号：US12640700

申请日：2009-12-17

Applicant: Li-Ping Huang ,  Chih-Hsiang Huang ,  Ka-Hing Fung ,  Chung-Cheng Wu ,  Haiting Wang

Inventor： Li-Ping Huang ,  Chih-Hsiang Huang ,  Ka-Hing Fung ,  Chung-Cheng Wu ,  Haiting Wang

IPC: H01L29/24 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/28123 ,  H01L21/823878 ,  H01L27/092

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition.

Abstract translation: 本发明提供集成电路。 集成电路包括具有第一组成的第一晶体管的第一操作装置; 第二操作装置，具有第一组合物的第二晶体管; 以及设置在所述第一和第二晶体管之间的隔离晶体管，所述隔离晶体管具有不同于所述第一组成的第二组成。

公开(公告)号：US07855586B2

公开(公告)日：2010-12-21

申请号：US12347074

申请日：2008-12-31

Applicant: Chen-Hsung Wang ,  Wei-Liang Kung ,  Chung-Cheng Wu

Inventor： Chen-Hsung Wang ,  Wei-Liang Kung ,  Chung-Cheng Wu

IPC: H03K3/017

CPC classification number: H03K3/017 ,  H03K3/84 ,  H03K4/502

Abstract: A frequency jitter generator and a frequency jitter PWM controller are provided for overcoming the shortcoming that a conventional PWM controller reduces the electromagnetic interference issue by means of varying the operating frequency of the PWM controller based on an input voltage, while resulting in the uncertainty of the range of frequency jitter and the difficulty circuit design due to the effect of the input voltage and the load. The frequency jitter generator and PWM controller adjust the range of frequency jitter by using a signal within a fixed voltage range. The invention not only gets rid of the effect of the input voltage and the loading, but also simplifies the circuit design by fixing the range of frequency jitter no greater than a predetermined percentage regardless of the operating frequency of the PWM controller.

Abstract translation: 提供了一种频率抖动发生器和频率抖动PWM控制器来克服传统PWM控制器通过基于输入电压改变PWM控制器的工作频率来减少电磁干扰问题的缺点，同时导致不确定性 由于输入电压和负载的影响，频率抖动范围和电路设计难度大。 频率抖动发生器和PWM控制器通过使用固定电压范围内的信号来调整频率抖动的范围。 本发明不仅消除了输入电压和负载的影响，而且通过将频率抖动的范围固定为不大于预定百分比来简化电路设计，而不管PWM控制器的工作频率如何。

公开(公告)号：US07109692B1

公开(公告)日：2006-09-19

申请号：US11286321

申请日：2005-11-25

Applicant: Chung-Cheng Wu ,  Qin Huang ,  Xiao-Ming Duan

Inventor： Chung-Cheng Wu ,  Qin Huang ,  Xiao-Ming Duan

IPC: G05F1/40

CPC classification number: H02M3/157 ,  H02M1/44 ,  H02M3/1563

Abstract: A high-speed PWM control apparatus with adaptive voltage position and a driving signal generating method thereof is provided. The present invention automatically detects a change in the loading and adjusts the voltage position instantaneously for stabilizing the voltage and reducing the loading output power consumption. The present invention does not require a clock signal to generate a driving signal and does not require an error amplifier to control the modulation. Therefore, the present invention has a fast transient response that responds to the change of the loading instantaneously and has a stabilizing effect. When the apparatus is on a continuous conduction mode (CCM), the switching frequency of the controller is still fixed even though the input voltage Vin and the output voltage Vout are changed. The electrical-magnetic noise disturbance is improved.

Abstract translation: 提供一种具有自适应电压位置的高速PWM控制装置及其驱动信号产生方法。 本发明自动检测负载变化并且瞬时调节电压位置以稳定电压并降低负载输出功率消耗。 本发明不需要时钟信号来产生驱动信号，并且不需要误差放大器来控制调制。 因此，本发明具有快速瞬时响应，其瞬时响应负载变化并且具有稳定效果。 当设备处于连续导通模式（CCM）时，即使输入电压Vin和输出电压Vout改变，控制器的开关频率仍然是固定的。 电磁噪声干扰得到改善。

公开(公告)号：US20060079068A1

公开(公告)日：2006-04-13

申请号：US11288858

申请日：2005-11-29

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L21/76

CPC classification number: H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

公开(公告)号：US20050161069A1

公开(公告)日：2005-07-28

申请号：US10762454

申请日：2004-01-23

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: E04H15/28 ,  E04H15/36

CPC classification number: E04H15/28

Abstract: A tent comprising a shaft, a protective cover, a handle and a plurality number of supporting ribs; the upper, lower shaft design and the supporting ribs is easy for storage; a running ring below the runner is on the upper shaft, two ropes connecting to the runner and running ring respectively stretch out from a cap and connect to an opening ring and a closing ring respectively as the open and close switches, a zipper door is on one side of the protective cover, a ground mats covering ground stretches from the bottom of the protective cover, the ground mats has a tri-directional zipper.

Abstract translation: 帐篷，包括轴，保护罩，手柄和多个支撑肋; 上，下轴设计和支撑肋容易存放; 跑道下方的跑步环位于上轴上，连接到跑步者和跑步环的两根绳子分别从盖子伸出，并分别连接到开环和闭合圈作为开闭开关，拉链门处于 保护罩的一侧，覆盖地面的地垫从保护罩的底部延伸，地垫具有三向拉链。