公开(公告)号：US08324668B2

公开(公告)日：2012-12-04

申请号：US12640700

申请日：2009-12-17

申请人： Li-Ping Huang ,  Chih-Hsiang Huang ,  Ka Hing Fung ,  Chung-Cheng Wu ,  Haiting Wang

发明人： Li-Ping Huang ,  Chih-Hsiang Huang ,  Ka Hing Fung ,  Chung-Cheng Wu ,  Haiting Wang

IPC分类号： H01L29/76

CPC分类号： H01L27/0207 ,  H01L21/28123 ,  H01L21/823878 ,  H01L27/092

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition.

摘要翻译： 本发明提供集成电路。 集成电路包括具有第一组成的第一晶体管的第一操作装置; 第二操作装置，具有第一组合物的第二晶体管; 以及设置在所述第一和第二晶体管之间的隔离晶体管，所述隔离晶体管具有不同于所述第一组成的第二组成。

公开(公告)号：US20110147765A1

公开(公告)日：2011-06-23

申请号：US12640700

申请日：2009-12-17

申请人： Li-Ping Huang ,  Chih-Hsiang Huang ,  Ka-Hing Fung ,  Chung-Cheng Wu ,  Haiting Wang

发明人： Li-Ping Huang ,  Chih-Hsiang Huang ,  Ka-Hing Fung ,  Chung-Cheng Wu ,  Haiting Wang

IPC分类号： H01L29/24 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L27/0207 ,  H01L21/28123 ,  H01L21/823878 ,  H01L27/092

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition.

摘要翻译： 本发明提供集成电路。 集成电路包括具有第一组成的第一晶体管的第一操作装置; 第二操作装置，具有第一组合物的第二晶体管; 以及设置在所述第一和第二晶体管之间的隔离晶体管，所述隔离晶体管具有不同于所述第一组成的第二组成。

公开(公告)号：US08482079B2

公开(公告)日：2013-07-09

申请号：US13161031

申请日：2011-06-15

申请人： Chun-Fai Cheng ,  Li-Ping Huang ,  Ka-Hing Fung

发明人： Chun-Fai Cheng ,  Li-Ping Huang ,  Ka-Hing Fung

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66666 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed device comprises a gate structure over a substrate and defining a channel region in the substrate, an epitaxial feature with a first dopant in the substrate, and an epitaxial source/drain feature with a second dopant in the substrate. The epitaxial source/drain feature is farther from the channel region than the epitaxial feature is. The second dopant has an electrical carrier type opposite to the first dopant.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的器件包括在衬底上的栅极结构并且限定衬底中的沟道区，在衬底中具有第一掺杂剂的外延特征以及在衬底中具有第二掺杂剂的外延源极/漏极特征。 外延源极/漏极特征比沟道区域远离外延特征。 第二掺杂剂具有与第一掺杂剂相反的电载体。

公开(公告)号：US09698054B2

公开(公告)日：2017-07-04

申请号：US12984703

申请日：2011-01-05

申请人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Li-Ping Huang ,  Wei-Yuan Lu

发明人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Li-Ping Huang ,  Wei-Yuan Lu

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636

摘要： In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity.

公开(公告)号：US08828817B2

公开(公告)日：2014-09-09

申请号：US13356207

申请日：2012-01-23

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC分类号： H01L21/8238

CPC分类号： H01L29/7849 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7613 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.

摘要翻译： 形成半导体器件的方法包括在衬底上执行第一预非晶体注入工艺，其中衬底具有栅叠层。 该方法还包括在衬底上形成第一应力膜。 该方法还包括对基板和第一应力膜执行第一退火处理。 该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。

公开(公告)号：US08348686B1

公开(公告)日：2013-01-08

申请号：US13270745

申请日：2011-10-11

申请人： Li-Ping Huang

发明人： Li-Ping Huang

IPC分类号： H01R13/44

CPC分类号： H01R13/6272 ,  H01R13/6392

摘要： A plug security structure includes a plug, a cable, a jacket, a movable cap and a key. By means of a middle block, the movable cap is slidably insertable into sliding grooves in between two upright sidewalls of a front bracket of the jacket to stop the front stop block and to have outer ribs of the elastic retaining members of the movable cap be stopped at rear end edges of the sliding grooves in the upright sidewalls of the front bracket, preventing the latch from downward displacement to unlock the plug from the mating jack and assuring a high level of network data transmission safeness. The cap has a raised portion for friction engagement with the bottom surface of the stop wall of the front bracket of the jacket, preventing vibration or displacement of the movable cap and assuring positive operation of the latch of the plug.

摘要翻译： 插头安全结构包括插头，电缆，护套，可动盖和钥匙。 通过中间块，可移动盖可滑动地插入到护套的前支架的两个直立侧壁之间的滑动槽中，以阻止前止动块并且使可动盖的弹性保持构件的外肋停止 在前支架的直立侧壁中的滑动槽的后端边缘处，防止闩锁向下移位，以使插头从配合插座解锁，并确保高水平的网络数据传输安全性。 盖具有用于与护套的前支架的止动壁的底表面摩擦接合的凸起部分，防止可动盖的振动或位移，并确保插头的闩锁的正向操作。

公开(公告)号：US07732877B2

公开(公告)日：2010-06-08

申请号：US11731963

申请日：2007-04-02

申请人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

发明人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/66356

摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

摘要翻译： 门控二极管半导体器件或类似部件及其制造方法。 该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且邻近源极和漏极。 源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。 这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。 如果两者都存在，则源极和漏极可以是对称的或非对称的。 这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

公开(公告)号：US20080237746A1

公开(公告)日：2008-10-02

申请号：US11731963

申请日：2007-04-02

申请人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

发明人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/66356

摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

摘要翻译： 门控二极管半导体器件或类似部件及其制造方法。 该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且与源极和漏极相邻。 源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。 这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。 如果两者都存在，则源极和漏极可以是对称的或非对称的。 这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

公开(公告)号：US20130187221A1

公开(公告)日：2013-07-25

申请号：US13356207

申请日：2012-01-23

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7849 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7613 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.

摘要翻译： 形成半导体器件的方法包括在衬底上执行第一预非晶体注入工艺，其中衬底具有栅叠层。 该方法还包括在衬底上形成第一应力膜。 该方法还包括对基板和第一应力膜执行第一退火处理。 该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。

公开(公告)号：US08273633B2

公开(公告)日：2012-09-25

申请号：US11690869

申请日：2007-03-26

申请人： Keh-Chiang Kuo ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

发明人： Keh-Chiang Kuo ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/2686 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823878

摘要： A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.

摘要翻译： 增加掺杂剂激活而不会受到额外的掺杂剂扩散的方法包括在半导体衬底中形成浅掺杂的和轻掺杂的源极/漏极扩展区，在源极/漏极延伸区上执行第一退火工艺，形成深和重掺杂的源/ 漏极区域，并且在源极/漏极区域上执行第二退火处理。 第一退火工艺是在约1毫秒至3毫秒之间的时间内执行的闪光退火工艺，第二退火工艺是在约1秒至30秒之间进行的快速热退火工艺。