公开(公告)号：US6063548A

公开(公告)日：2000-05-16

申请号：US148565

申请日：1998-09-04

Applicant: Wen-Ting Chu ,  Chung-Cheng Wu

Inventor： Wen-Ting Chu ,  Chung-Cheng Wu

IPC: H01L21/02 ,  H01L21/8242 ,  G03C5/00

CPC classification number: H01L28/92 ,  H01L27/10852

Abstract: A method for forming stacked capacitors for DRAMs using a single photoresist mask and having bottom electrodes self-aligned to node contacts is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. A first silicon nitride (Si.sub.3 N.sub.4) hard mask layer is deposited and a second insulating layer is deposited. First openings are etched, partially into the first insulating layer, for the capacitor bottom electrodes. A second Si.sub.3 N.sub.4 layer is deposited and etched back to form sidewall spacers in the first openings. The Si.sub.3 N.sub.4 hard mask and spacers are used to etch second openings (node contacts) in the first insulating layer, self-aligned in the first openings and to the source/drain contact areas. A first polysilicon layer is deposited and etched back to form recessed polysilicon plugs in the first openings. A third Si.sub.3 N.sub.4 layer is deposited and etched back to form sidewall spacers on the plugs in the first openings and is used as a mask to etch the polysilicon to form the vertical sidewalls of the bottom electrodes self-aligned to the node contacts. The first insulating layer is recessed to expose the bottom electrodes. An interelectrode dielectric layer is formed on the bottom electrodes, and a patterned second polysilicon layer is used for the top electrodes.

Abstract translation: 实现了使用单个光致抗蚀剂掩模形成用于DRAM的堆叠电容器并且具有与节点接触自对准的底部电极的方法。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层。 沉积第一氮化硅（Si 3 N 4）硬掩模层并沉积第二绝缘层。 对于电容器底部电极，第一开口部分地被蚀刻到第一绝缘层中。 第二Si 3 N 4层被沉积并回蚀刻以在第一开口中形成侧壁间隔物。 Si 3 N 4硬掩模和间隔物用于蚀刻第一绝缘层中的第二开口（节点接触），在第一开口中和源/漏接触区域中自对准。 沉积第一多晶硅层并将其回蚀刻以在第一开口中形成凹陷的多晶硅塞。 沉积第三个Si 3 N 4层并回蚀刻以在第一开口中的插塞上形成侧壁间隔物，并且用作掩模以蚀刻多晶硅以形成与节点接触件自对准的底部电极的垂直侧壁。 第一绝缘层凹进露出底部电极。 在底部电极上形成电极间电介质层，并且将图案化的第二多晶硅层用于顶部电极。

公开(公告)号：US20060115938A1

公开(公告)日：2006-06-01

申请号：US11001514

申请日：2004-11-30

Applicant: Chung-Cheng Wu ,  Wen-Ting Chu

Inventor： Chung-Cheng Wu ,  Wen-Ting Chu

IPC: H01L21/338

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L29/42376 ,  H01L29/66575

Abstract: A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.

Abstract translation: 一种T形栅极结构及其形成方法，包括提供包括至少一个上覆牺牲层的半导体衬底; 光刻地图案化覆盖至少一个牺牲层的抗蚀剂层，以蚀刻开口; 通过所述至少一个牺牲层的厚度形成所述蚀刻开口以暴露所述半导体衬底，所述蚀刻开口包括与底部相比具有较宽上部的锥形横截面; 并且用栅电极材料回填蚀刻的开口以形成栅极结构。

公开(公告)号：US07749911B2

公开(公告)日：2010-07-06

申请号：US11001514

申请日：2004-11-30

Applicant: Chung-Cheng Wu ,  Wen-Ting Chu

Inventor： Chung-Cheng Wu ,  Wen-Ting Chu

IPC: H01L21/311

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L29/42376 ,  H01L29/66575

Abstract: A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.

Abstract translation: 一种T形栅极结构及其形成方法，包括提供包括至少一个上覆牺牲层的半导体衬底; 光刻地图案化覆盖至少一个牺牲层的抗蚀剂层，以蚀刻开口; 通过所述至少一个牺牲层的厚度形成所述蚀刻开口以暴露所述半导体衬底，所述蚀刻开口包括与底部相比具有较宽上部的锥形横截面; 并且用栅电极材料回填蚀刻的开口以形成栅极结构。

公开(公告)号：US20140021584A1

公开(公告)日：2014-01-23

申请号：US13553086

申请日：2012-07-19

Applicant: Kuo-Chi Tu ,  Wen-Ting Chu

Inventor： Kuo-Chi Tu ,  Wen-Ting Chu

IPC: H01L29/86 ,  H01L21/02

CPC classification number: H01L23/5223 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L28/40 ,  H01L29/94 ,  H01L45/04 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

Abstract translation: 提供去耦电容器件。 去耦电容器装置包括在沉积工艺中沉积的第一电介质层部分，其沉积用于非易失性存储单元的第二电介质层部分。 使用单个掩模对两个部分进行图案化。 还提供了片上系统（SOC）器件，SOC包括位于单个金属间介电层中的RRAM单元和去耦电容器。 还提供了一种形成工艺兼容去耦电容器的方法。 该方法包括图案化顶部电极层，绝缘层和底部电极层，以形成非易失性存储元件和去耦电容器。

公开(公告)号：US08124494B2

公开(公告)日：2012-02-28

申请号：US11778558

申请日：2007-07-16

Applicant: Yu-Hsiung Wang ,  Wen-Ting Chu ,  Eric Chen ,  Hsien-Wei Chin

Inventor： Yu-Hsiung Wang ,  Wen-Ting Chu ,  Eric Chen ,  Hsien-Wei Chin

IPC: H01L21/76

CPC classification number: H01L29/7833 ,  H01L21/76224

Abstract: A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process.

Abstract translation: 提出了一种通过用牺牲层重塑硅表面来制造半导体器件的方法。 在本发明中，形成牺牲电介质层和去除牺牲电介质层的步骤被重复多次，以便从场氧化物附近的硅表面去除尖锐的边缘。 本发明的另一方面包括制造一种MOSFET晶体管，其将多个牺牲层的形成和去除结合到该工艺中。

公开(公告)号：US07667261B2

公开(公告)日：2010-02-23

申请号：US11785382

申请日：2007-04-17

Applicant: Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

Abstract translation: 分离栅存储单元及其制造方法。 分离栅存储器单元包括沿着第一方向在半导体衬底上形成的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

公开(公告)号：US07652318B2

公开(公告)日：2010-01-26

申请号：US11592290

申请日：2006-11-03

Applicant: Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

Abstract translation: 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

公开(公告)号：US07385244B2

公开(公告)日：2008-06-10

申请号：US11051845

申请日：2005-02-03

Applicant: Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

Inventor： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324

Abstract: A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.

Abstract translation: 一种在多晶硅蚀刻工艺中形成改进的蚀刻硬掩模氧化物层的方法，包括提供包括相邻的第一裸露多晶硅部分和暴露的氧化物部分的平坦化的半导体晶片工艺表面; 选择性地蚀刻暴露的氧化物部分的厚度部分; 在暴露的多晶硅部分上热生长氧化物硬掩模层以形成氧化物硬掩模部分; 暴露出与至少一个氧化物硬掩模部分相邻的第二暴露的多晶硅部分; 并且蚀刻穿过第二暴露的多晶硅部分的厚度部分。

公开(公告)号：US20070205436A1

公开(公告)日：2007-09-06

申请号：US11368714

申请日：2006-03-06

Applicant: Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

Inventor： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

IPC: H01L29/76

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

Abstract: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

Abstract translation: 分离门存储单元。 浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。 浮栅设置在一对隔离结构之间，并且不与其上表面重叠。 盖层设置在浮动栅上。 控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。 源极区域形成在靠近浮动栅极一侧的衬底中。

公开(公告)号：US07106629B2

公开(公告)日：2006-09-12

申请号：US10788949

申请日：2004-02-27

Applicant: Wen-Ting Chu ,  Chia-Ta Hsieh

Inventor： Wen-Ting Chu ,  Chia-Ta Hsieh

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

Abstract: A split-gate, P-channel flash memory cell having a band-to-band hot electron (BBHE) programming method is defined to improve the endurance characteristics of performance of the cell. The split-gate, P-channel structure, which includes a P+ drain, P+ source, floating gate and a control gate, advantageously improves protection from over-erase and hot-hole trap conditions, and improves programming speed and higher injection efficiency. The cell is erased by a polysilicon-polysilicon tunneling technique.

Abstract translation: 定义了具有带 - 带热电子（BBHE）编程方法的分裂门P通道快闪存储器单元，以提高电池性能的耐久特性。 包括P +漏极，P +源极，浮动栅极和控制栅极的分离栅极P沟道结构有利地提高了对过度擦除和热阱阱条件的保护，并提高了编程速度和更高的注入效率。 电池被多晶硅多晶硅隧道技术擦除。