公开(公告)号：US06266272B1

公开(公告)日：2001-07-24

申请号：US09364841

申请日：1999-07-30

申请人： Toshiaki Kirihata ,  Daniel Storaska ,  Chandrasekhar Narayan ,  William Tonti ,  Claude Bertin ,  Nick van Heel

发明人： Toshiaki Kirihata ,  Daniel Storaska ,  Chandrasekhar Narayan ,  William Tonti ,  Claude Bertin ,  Nick van Heel

IPC分类号： G11C1450

CPC分类号： G11C16/02 ,  G11C11/005

摘要： A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.

摘要翻译： 部分非易失性动态随机存取存储器（PNDRAM）使用由多个单晶体管（1T）单元或两个晶体管（2T）单元形成的DRAM阵列。 电池可电可编程为非易失性存储器。 这导致具有动态随机存取存储器（DRAM）和电可编程只读存储器（EPROM）的单芯片设计。 集成在PNDRAM中的DRAM和EPROM可以随时重新配置，无论是在制造还是在现场。 PNDRAM具有多个应用，例如将主内存与ID，BIOS或操作系统信息组合在一个芯片中。

公开(公告)号：US20060289864A1

公开(公告)日：2006-12-28

申请号：US11482688

申请日：2006-07-07

申请人： John Fifield ,  Russell Houghton ,  William Tonti

发明人： John Fifield ,  Russell Houghton ,  William Tonti

IPC分类号： H01L29/04 ,  H01L29/74 ,  H01L29/76 ,  H01L29/00 ,  H01L23/62

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/957 ,  H01L2924/00

摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

公开(公告)号：US20070284669A1

公开(公告)日：2007-12-13

申请号：US11838934

申请日：2007-08-15

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： B07C5/344 ,  G01R31/2831

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

公开(公告)号：US20070241768A1

公开(公告)日：2007-10-18

申请号：US11760575

申请日：2007-06-08

申请人： KARL ERICKSON ,  John Fifield ,  Chandrasekharan Kothandaraman ,  Phil Paone ,  William Tonti

发明人： KARL ERICKSON ,  John Fifield ,  Chandrasekharan Kothandaraman ,  Phil Paone ,  William Tonti

IPC分类号： G11C8/20

CPC分类号： G06F21/71

摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).

摘要翻译： 提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。 操作和/或访问可以基于存储在诸如电可编程熔丝（eFUSES）的非易失性存储元件中的值来提供。

公开(公告)号：US20070190740A1

公开(公告)日：2007-08-16

申请号：US11733249

申请日：2007-04-10

申请人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

发明人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

IPC分类号： H01L21/76

CPC分类号： H01L29/78687 ,  H01L21/26533 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78603

摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.

摘要翻译： 提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。 增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。 在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

公开(公告)号：US20070102766A1

公开(公告)日：2007-05-10

申请号：US11163966

申请日：2005-11-04

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  William Tonti

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  William Tonti

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114

摘要： A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

摘要翻译： 一种结构及其形成方法。 该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个 层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。

公开(公告)号：US20070018280A1

公开(公告)日：2007-01-25

申请号：US11527343

申请日：2006-09-26

申请人： William Motsiff ,  William Tonti ,  Richard Williams

发明人： William Motsiff ,  William Tonti ,  Richard Williams

IPC分类号： H01L29/00 ,  H01L21/326

CPC分类号： H01L23/5252 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

摘要翻译： 一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。 在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。 将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。 脉冲激光能量软化金属片段，静电场使金属片段彼此接触。 静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。

公开(公告)号：US20060220174A1

公开(公告)日：2006-10-05

申请号：US11440199

申请日：2006-05-24

申请人： Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features of the mask, a second method uses a photolithographic mask with a sub-minimum widthwise jog or offset between minimum size pattern features of the mask, and a third method is a combination of the first and second methods. Each of the three methods can be used with three different embodiments, a first embodiment is a polysilicon E-Fuse with a sub-minimum width polysilicon fuse line, a second embodiment is a work function altered/programmed self-aligned MOSFET E-Fuse with a sub-minimum width fuse line, and a third embodiment is a polysilicon MOSFET E-Fuse with a sub-minimum width fuse line which is programmed with a low trigger voltage snapback.

摘要翻译： 使用标准光刻法来图案化和制造最终的多晶硅晶片成像结构，该结构小于正常允许光刻最小尺寸。 提供了三种不同的方法来产生这样的次最小维度结构，第一种方法使用具有掩模的最小尺寸图案特征之间的亚最小空间的光刻掩模，第二种方法使用光刻掩模与次最小宽度方向点动 或掩模的最小尺寸图案特征之间的偏移，第三种方法是第一和第二方法的组合。 三种方法中的每一种可以与三种不同的实施例一起使用，第一实施例是具有亚最小宽度多晶硅熔丝线的多晶硅E熔丝，第二实施例是工作功能改变/编程的自对准MOSFET E-Fuse，具有 亚最小宽度熔丝线，第三实施例是具有低电平触发电压快速编程的亚最小宽度熔丝线的多晶硅MOSFET E-Fuse。

公开(公告)号：US20060136751A1

公开(公告)日：2006-06-22

申请号：US11016219

申请日：2004-12-17

申请人： Anthony Bonaccio ,  Karl Erickson ,  John Fifield ,  Chandrasekharan Kothandaraman ,  Phil Paone ,  William Tonti

发明人： Anthony Bonaccio ,  Karl Erickson ,  John Fifield ,  Chandrasekharan Kothandaraman ,  Phil Paone ,  William Tonti

IPC分类号： G06F12/14

CPC分类号： G06F12/1433 ,  G06F21/6245

摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

公开(公告)号：US20050287718A1

公开(公告)日：2005-12-29

申请号：US10710256

申请日：2004-06-29

申请人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/00 ,  H01L21/334 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1087 ,  H01L27/1203

摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

摘要翻译： 本发明提供了一种在本体硅区域中的指状去耦电容器，其通过在本体硅区域中蚀刻一系列最小或次最小沟槽而形成，氧化这些沟槽，从至少一个或多个不相交的沟槽中去除氧化物， 具有原位掺杂多晶硅的沟槽，后来通过离子注入掺杂的本征多晶硅，或者用金属柱（例如钨）填充并形成标准互连到电容器板。