公开(公告)号：US20080137397A1

公开(公告)日：2008-06-12

申请号：US12019746

申请日：2008-01-25

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger

IPC分类号： G11C13/00 ,  H01L21/82 ,  G11C11/34

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/16 ,  G11C2213/77 ,  Y10S977/742 ,  Y10S977/939 ,  Y10S977/943

摘要： Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

摘要翻译： 使用垂直纳米管的非易失性和辐射硬的开关和存储器件，并通过范德华力力可逆地保持状态和制造器件的方法。 用于感测装置状态的装置包括测量电容，以及隧穿和场发射电流。

公开(公告)号：US07385839B2

公开(公告)日：2008-06-10

申请号：US11275010

申请日：2005-12-01

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

IPC分类号： G11C11/00

CPC分类号： G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512

摘要： Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

摘要翻译： 结构和操作方法。 该结构包括（a）基底; （b）基板上的第一和第二电极区域; 和（c）设置在第一和第二电极区之间的第三电极区。 响应于施加在第一和第三电极区域之间的第一写入电压电位，第三电极区域改变其自身形状，使得响应于随后施加在第一和第三电极区域之间的预先指定的读取电压电势，感测 电流在第一和第三电极区域之间流动。 此外，响应于施加在第二和第三电极区域之间的第二写入电压电位，第三电极区域改变其自身形状，使得响应于施加在第一和第三电极区域之间的预先设定的读取电压电位， 所述感测电流不在第一和第三电极区域之间流动。

公开(公告)号：US07264415B2

公开(公告)日：2007-09-04

申请号：US10798908

申请日：2004-03-11

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： G03F1/00 ,  G03C5/00

CPC分类号： G03F1/30

摘要： Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

摘要翻译： 用于制造用于半导体光刻系统中的交替相移掩模或掩模版的方法。 所述方法通常包括在手柄基板上形成一层相移掩模材料，并且图案化该层以限定凹陷的相移窗口。 图案层从手柄晶片转移到掩模板。 相移窗口的深度由相移掩模材料层的厚度确定，并且与图案化工艺无关。 特别地，相移窗口的深度不依赖于通过掩模板的表面的蚀刻工艺的蚀刻速率均匀性。

公开(公告)号：US07102201B2

公开(公告)日：2006-09-05

申请号：US10892467

申请日：2004-07-15

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).

摘要翻译： 半导体制造方法和结构，器件和集成电路，其特征在于增强的操作性能。 结构通常包括形成在半导体材料的主体中的第一和第二源极/漏极区域以及限定在第一和第二源极/漏极区域之间的主体中的沟道区域。 在第一和第二源极/漏极区域中的至少一个中设置有多个插塞，每个插塞由容积扩大的材料形成，该压缩应力向沟道区域传递压缩应力。 压缩应变通道区域可能是有用的，例如，用于改善p沟道场效应晶体管（PFET）的操作性能。

公开(公告)号：US06891235B1

公开(公告)日：2005-05-10

申请号：US09713830

申请日：2000-11-15

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Edward Joseph Nowak

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Edward Joseph Nowak

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/7833

摘要： An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.

摘要翻译： FET具有T形栅极。 FET具有与T的底部自对准的晕圈扩散，并且与顶部自对准的延伸扩散。 因此，光环与延伸植入物分离，这提供了显着的优点。 T形门的顶部和底部可以由两种不同材料的层形成，例如锗和硅。 两层被图案化在一起。 然后，底层的暴露边缘被选择性地化学反应，并且蚀刻掉反应产物以提供凹口。 在另一个实施例中，栅极由单个栅极导体形成。 金属沿着侧壁共形沉积，凹陷蚀刻以暴露侧壁的顶部，并且被加热以沿底部形成硅化物。 蚀刻硅化物以提供凹口。

公开(公告)号：US06875703B1

公开(公告)日：2005-04-05

申请号：US10760500

申请日：2004-01-20

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132

摘要： A method is provided for forming a quadruple density sidewall image transfer (SIT) structure. Oxide spacers are formed on opposite sidewalls of a first mandrel. The oxide spacers form a second mandrel. Then sidewall spacers are formed on opposite sidewalls of the oxide spacers forming the second mandrel. A pattern of the sidewall spacers is used to form the quadruple density sidewall image transfer (SIT) structure. The method of the invention enables formation of four well-controlled lines for each lithographically minimum pitch dimension.

摘要翻译： 提供了一种用于形成四重密度侧壁图像转印（SIT）结构的方法。 氧化物间隔件形成在第一心轴的相对侧壁上。 氧化物间隔物形成第二心轴。 然后，侧壁间隔件形成在形成第二心轴的氧化物间隔件的相对侧壁上。 侧壁间隔物的图案用于形成四重密度侧壁图像转印（SIT）结构。 本发明的方法能够形成用于每个光刻最小间距尺寸的四个良好控制的线。

公开(公告)号：US06342323B1

公开(公告)日：2002-01-29

申请号：US09523796

申请日：2000-03-13

申请人： William Hsioh-Lien Ma ,  David Vaclay Horak ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Mark Charles Hakey

发明人： William Hsioh-Lien Ma ,  David Vaclay Horak ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Mark Charles Hakey

IPC分类号： G03F900

CPC分类号： G03F9/7084 ,  G03F9/7046

摘要： An improved alignment methodology for lithography. In the method, a third level is aligned to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions. A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.

摘要翻译： 改进光刻对准方法。 在该方法中，第三级与两个先前级别对准，其中基于x和y方向上的两个先前级别来计算第三级的对准标记位置。 本发明的优选实施例涉及一种用于使半导体器件的第三级相对于器件的第一和第二级别对准的光刻对准方法。 该方法包括以下步骤：分别在第一和第二电平处形成第一和第二图案，以及确定两个原始方向上的第一和第二图案的偏移。 然后基于第一和第二图案的偏移的平均值来确定第三级中的第三图案的最佳位置。

公开(公告)号：US07435653B2

公开(公告)日：2008-10-14

申请号：US11735075

申请日：2007-04-13

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

公开(公告)号：US20080206996A1

公开(公告)日：2008-08-28

申请号：US11680204

申请日：2007-02-28

申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger

发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

摘要： A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD

摘要翻译： 同时形成多个线宽的方法，其中之一小于使用常规光刻技术可实现的线宽。 该方法包括提供在存储层顶部包括存储层和侧壁图像传输（SIT）层的结构。 然后，对SIT层进行图案化，形成SIT区域。 然后，在存储层的定向蚀刻期间，将SIT区域用作阻挡掩模，产生第一存储区域。 然后，SIT区域的侧壁在参考方向上退回退避距离D，导致SIT部分。 所述图案化包括光刻工艺。 退回距离D小于与光刻工艺相关联的关键尺寸CD。 SIT区域包括参考方向上的第一维W 2和第二维W 3，其中CD

公开(公告)号：US07271444B2

公开(公告)日：2007-09-18

申请号：US10732958

申请日：2003-12-11

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L29/76

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。