公开(公告)号：US5619662A

公开(公告)日：1997-04-08

申请号：US289613

申请日：1994-08-12

申请人： Simon C. Steely, Jr. ,  David J. Sager ,  David B. Fite, Jr.

发明人： Simon C. Steely, Jr. ,  David J. Sager ,  David B. Fite, Jr.

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3863 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3848 ,  G06F9/3855 ,  G06F9/3857

摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

摘要翻译： 流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从指令处理器重新排序指令集的发布。 映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。 处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。 处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

公开(公告)号：US5564118A

公开(公告)日：1996-10-08

申请号：US352291

申请日：1994-12-08

申请人： Simon C. Steely, Jr. ,  David J. Sager ,  William B. Noyce

发明人： Simon C. Steely, Jr. ,  David J. Sager ,  William B. Noyce

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F9/40

CPC分类号： G06F9/3806 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3848 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

摘要翻译： 流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由所述指令组馈送的指令调度器，以从所述指令处理器重新排序所述指令集的发布。 映射的寄存器操作数字段在指令发布之前与所述重新排序的指令集的相应指令相关联。 处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。 处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

公开(公告)号：US5519841A

公开(公告)日：1996-05-21

申请号：US974776

申请日：1992-11-12

申请人： David J. Sager ,  Simon C. Steely, Jr. ,  David B. Fite, Jr.

发明人： David J. Sager ,  Simon C. Steely, Jr. ,  David B. Fite, Jr.

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/34

CPC分类号： G06F9/3863 ,  G06F9/32 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3848 ,  G06F9/3855 ,  G06F9/3857

摘要： A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

摘要翻译： 流水线处理器包括指令单元，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从处理器重新排序指令集的发布。 映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。 处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。 处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

公开(公告)号：US5421022A

公开(公告)日：1995-05-30

申请号：US79309

申请日：1993-06-17

申请人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowney

发明人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowney

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/312 ,  G06F9/42 ,  G06F9/44

CPC分类号： G06F9/3865 ,  G06F9/3842

摘要： A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition is detected and the set of instructions is re-executed in a real state of the computer system to resolve the exception condition.

摘要翻译： 编译器将指令分组成集合。 指令集是由编译器无法解决的数据和控制依赖关系相关的。 在具有未解决的依赖性的指令集在假定不发生异常条件的假设下在计算机系统的推测状态下执行。 然而，如果在推测状态下执行一组指令时发生异常情况，则检测该异常条件，并且在计算机系统的实际状态中重新执行指令集以解决异常状况。

公开(公告)号：US5003537A

公开(公告)日：1991-03-26

申请号：US369768

申请日：1989-06-22

申请人： David J. Sager

发明人： David J. Sager

IPC分类号： G06F1/10 ,  H04L7/00

CPC分类号： H04L7/0008 ,  G06F1/10

摘要： The invention expands the period of data stabilization between state devices to be 1.5 times the cycle time minus the clock skew. The invention requires that a clock signal (hereinafter "forwarded clock") be sent with data to the receiving subsystem. Such data is received by a capture latch, which is operated by special logic that receives the forwarded clock, and then proceeds to an ordinary state device in the receiving subsystem that is running synchronously with the receiving subsystem. This state device nominally captures the data 1.5 cycles after it was sent from a state device in the sending subsystem.

摘要翻译： 本发明将状态设备之间的数据稳定期延长为周期时间的1.5倍减去时钟偏移。 本发明要求将时钟信号（以下称为“转发时钟”）与数据一起发送到接收子系统。 这样的数据由捕获锁存器接收，捕获锁存器由接收转发的时钟的特殊逻辑操作，然后进行到与接收子系统同步运行的接收子系统中的普通状态设备。 该状态设备在从发送子系统中的状态设备发送后的1.5个周期内名义上捕获数据。

公开(公告)号：US5003459A

公开(公告)日：1991-03-26

申请号：US176595

申请日：1988-04-01

申请人： Raj K. Ramanujan ,  Simon C. Steely, Jr. ,  Peter J. Bannon ,  David J. Sager

发明人： Raj K. Ramanujan ,  Simon C. Steely, Jr. ,  Peter J. Bannon ,  David J. Sager

IPC分类号： G06F12/10

CPC分类号： G06F12/1045

摘要： The invention is directed to a cache memory system in a data processor including a virtual cache memory, a physical cache memory, a virtual to physical translation buffer, a physical to virtual backmap, an Old-PA pointer and a lockout register. The backmap implements invalidates by clearing the valid flags in virtual cache memory. The Old-PA pointer indicates the backmap entry to be invalidated after a reference misses in the virtual cache. The physical address for data written to virtual cache memory is entered to Old-PA pointer by the translation buffer. The lockout register arrests all references to data which may have synonyms in virtual cache memory. The backmap is also used to invalidate any synonyms.

摘要翻译： 本发明涉及包括虚拟高速缓冲存储器，物理高速缓冲存储器，虚拟到物理转换缓冲器，物理到虚拟背景图，旧PA指针和锁定寄存器的数据处理器中的高速缓冲存储器系统。 反向映射通过清除虚拟高速缓存中的有效标志来实现无效。 Old-PA指针指示在虚拟缓存中的引用未命中之后，将无效的背景条目。 写入虚拟高速缓冲存储器的数据的物理地址由转换缓冲区输入到旧PA指针。 锁定寄存器阻止对虚拟高速缓冲存储器中可能具有同义词的数据的所有引用。 背景图也用于使任何同义词无效。

公开(公告)号：US20110208918A1

公开(公告)日：2011-08-25

申请号：US12978513

申请日：2010-12-24

申请人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

发明人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/30032 ,  G06F9/3824 ,  G06F9/384 ,  Y02D10/13

摘要： Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

摘要翻译： 描述与硬件移动消除和/或下一页预取相关的方法和装置。 在一些实施例中，逻辑可以基于存储的数据提供硬件移动消除。 在一个实施例中，公开了下一页预取器。 还描述和要求保护其他实施例。

公开(公告)号：US07100012B2

公开(公告)日：2006-08-29

申请号：US10629244

申请日：2003-07-28

申请人： David J. Sager

发明人： David J. Sager

IPC分类号： G06F13/00 ,  G06F1/04

CPC分类号： G06F12/0893 ,  G06F9/383 ,  G06F9/3863

摘要： A processor includes a cache memory with a data storage unit operating at a first clock frequency, and a tag unit and hit/miss logic operating at a second clock frequency different than the first clock frequency. The data storage unit may advantageously be clocked faster than the tag unit and hit/miss logic, such as two times (2×) faster. The processor may also include a replay mechanism for recovering from data speculation when the hit/miss logic or the tag unit signals that speculated data from the higher clocked data storage unit is, in fact, invalid.

公开(公告)号：US06928647B2

公开(公告)日：2005-08-09

申请号：US10365918

申请日：2003-02-13

申请人： David J. Sager

发明人： David J. Sager

IPC分类号： G06F9/48 ,  G06F15/16

CPC分类号： G06F9/4831 ,  G06F9/4881

摘要： The present invention provides a method and apparatus for controlling a processing priority assigned alternately to a first thread and a second thread in a multithreaded processor to prevent deadlock and livelock problems between the first thread and the second thread. In one embodiment, the processing priority is initially assigned to the first thread for a first duration. It is then determined whether the first duration has expired in a given processing cycle. If the first duration has expired, the processing priority is assigned to the second thread for a second duration.

摘要翻译： 本发明提供一种方法和装置，用于控制在多线程处理器中交替地分配给第一线程和第二线程的处理优先级，以防止第一线程和第二线程之间的死锁和动态锁定问题。 在一个实施例中，处理优先级最初在第一持续时间内被分配给第一线程。 然后在给定的处理周期中确定第一持续时间是否已经过期。 如果第一持续时间已经过期，则处理优先级被分配给第二个线程持续第二个持续时间。

公开(公告)号：US06785803B1

公开(公告)日：2004-08-31

申请号：US09667248

申请日：2000-09-22

申请人： Amit A. Merchant ,  David J. Sager ,  James D. Allen

发明人： Amit A. Merchant ,  David J. Sager ,  James D. Allen

IPC分类号： G06F938

CPC分类号： G06F9/3851 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3869

摘要： A technique is provided for breaking a stalled condition or livelock in a processor having a replay queue. A livelock or stalled condition is detected. One or more instructions are temporarily stored in a replay queue. A release or break in the livelock or stalled condition is detected, and the instructions are then unloaded from the replay queue for replay or re-execution. For a multi-threaded processor, a stall is detected in one of the threads. Instructions of the stalled thread are temporarily stored in a replay queue, except the oldest instruction of the stalled thread which is allowed to replay or re-execute. This allows other threads to have access to execution and replay resources. Eventually, the oldest instruction will execute and retire, which breaks or releases the stalled thread. The instructions stored in the replay queue are then unloaded from the replay queue.

摘要翻译： 提供了一种用于在具有重放队列的处理器中破坏停顿状态或活动锁定的技术。 检测到活动锁定或失速状态。 一个或多个指令临时存储在重播队列中。 检测到活动锁定或停止状态的释放或中断，然后从重放队列中卸载指令以进行重放或重新执行。 对于多线程处理器，在其中一个线程中检测到失速。 被停止的线程的指令被暂时存储在重放队列中，除了被允许重放或重新执行的被停止的线程的最旧的指令之外。 这允许其他线程访问执行和重播资源。 最后，最老的指令将执行并退出，从而中断或释放已停止的线程。 然后从重放队列中卸载存储在重放队列中的指令。