公开(公告)号：US08112680B2

公开(公告)日：2012-02-07

申请号：US12044183

申请日：2008-03-07

申请人： Hoe-Ju Chung ,  Jung-Bae Lee

发明人： Hoe-Ju Chung ,  Jung-Bae Lee

IPC分类号： G06F11/00

CPC分类号： G06F11/1008 ,  G11C5/02 ,  G11C5/04 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1045 ,  G11C2029/0411 ,  H04L1/0041 ,  H04L1/0057

摘要： A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.

摘要翻译： 系统，设备和相关方法用于经由包括所选择的数据通道的多个数据通道来传送数据。 在第一操作模式中，经由包括所选择的数据通道的多个数据通道来传送有效载荷数据和相关的补充数据。 在第二种操作模式中，只有有效载荷数据经由多个数据通道被传送，除了所选择的数据通道。

公开(公告)号：US07936196B2

公开(公告)日：2011-05-03

申请号：US12716373

申请日：2010-03-03

申请人： Jun Bae Kim ,  Chang-Hyun Bae ,  Jung-Bae Lee

发明人： Jun Bae Kim ,  Chang-Hyun Bae ,  Jung-Bae Lee

IPC分类号： H03L7/06

CPC分类号： G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/091 ,  H03L7/10

摘要： According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.

摘要翻译： 根据一个实施例，公开了一种在延迟锁定环电路中执行快速锁定的方法。 该方法包括执行将输入时钟信号与作为非反相反馈时钟信号的第一反馈时钟信号进行比较的第一比较，以及将输入时钟信号与作为反馈时钟信号的第二反馈时钟信号进行比较的第二比较 倒。 该方法还包括基于第一和第二比较，选择非反相反馈时钟信号或反相反馈时钟信号中的一个与输入时钟信号同步。 此外，该方法包括使所选择的时钟信号与输入时钟信号同步。

公开(公告)号：US20100226188A1

公开(公告)日：2010-09-09

申请号：US12716373

申请日：2010-03-03

申请人： Jun Bae Kim ,  Chang-Hyun Bae ,  Jung-Bae Lee

发明人： Jun Bae Kim ,  Chang-Hyun Bae ,  Jung-Bae Lee

IPC分类号： G11C7/00 ,  H03L7/06

CPC分类号： G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/091 ,  H03L7/10

摘要： According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.

摘要翻译： 根据一个实施例，公开了一种在延迟锁定环电路中执行快速锁定的方法。 该方法包括执行将输入时钟信号与作为非反相反馈时钟信号的第一反馈时钟信号进行比较的第一比较，以及将输入时钟信号与作为反馈时钟信号的第二反馈时钟信号进行比较的第二比较 倒。 该方法还包括基于第一和第二比较，选择非反相反馈时钟信号或反相反馈时钟信号之一以与输入时钟信号同步。 此外，该方法包括使所选择的时钟信号与输入时钟信号同步。

公开(公告)号：US20100157709A1

公开(公告)日：2010-06-24

申请号：US12589674

申请日：2009-10-27

申请人： Ho-Young Kim ,  Jung-Bae Lee

发明人： Ho-Young Kim ,  Jung-Bae Lee

IPC分类号： G11C7/04 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C29/02 ,  G11C5/143 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C29/028 ,  G11C2029/5002 ,  G11C2207/2254

摘要： A semiconductor memory device includes a plurality of memory banks; a plurality of temperature sensing circuits, and a shared control circuit. The temperature sensing circuits correspond to the memory banks and each is disposed in the vicinity of a corresponding memory bank. The shared control circuit is connected to the plurality of temperature sensing circuits and a plurality of refresh circuits for refreshing the plurality of memory banks, performs calibration on the plurality of temperature sensing circuits, performs digital processing on signals for separately controlling refresh intervals for the plurality of memory banks, and transmits the processed signals to the plurality of refresh circuits. Therefore, the refresh intervals for individual channels or banks are separately or selectively controlled. Further, since the plurality of temperature sensing circuits are connected to the shared temperature control circuit, the occupied area of the circuits in a chip is reduced or minimized.

摘要翻译： 半导体存储器件包括多个存储体; 多个温度检测电路和共享控制电路。 温度感测电路对应于存储体，并且各自设置在相应的存储体的附近。 共享控制电路连接到多个温度检测电路和多个刷新电路，用于刷新多个存储体，对多个温度感测电路进行校准，对用于分别控制多个温度感测电路的刷新间隔的信号执行数字处理 的存储体，并且将处理的信号发送到多个刷新电路。 因此，单独或选择性地控制各通道或组的刷新间隔。 此外，由于多个温度检测电路连接到共享温度控制电路，芯片中的电路的占用面积减小或最小化。

公开(公告)号：US20100018760A1

公开(公告)日：2010-01-28

申请号：US12458874

申请日：2009-07-27

申请人： Ki-Whan Song ,  Jung-Bae Lee

发明人： Ki-Whan Song ,  Jung-Bae Lee

IPC分类号： H03K3/01 ,  H05K1/16

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a first substrate including at least one first well region and first impurity regions on portions of the substrate and a bias voltage plate on a surface of the substrate. A semiconductor device may be of a three dimensional stack structure, and in example embodiments, the semiconductor device may further include a through contact plug substantially perpendicularly penetrating at least one substrate and at least one bias voltage plate. Therefore, a design margin of a semiconductor device may be enhanced and a bias voltage may be provided reliably.

摘要翻译： 半导体器件包括：第一衬底，包括至少一个第一阱区域和衬底的部分上的第一杂质区域以及衬底表面上的偏压板。 半导体器件可以是三维堆叠结构，并且在示例性实施例中，半导体器件还可以包括基本垂直地穿透至少一个衬底和至少一个偏置电压板的贯穿接触插塞。 因此，可以提高半导体器件的设计裕度，并且可以可靠地提供偏置电压。

公开(公告)号：US07447862B2

公开(公告)日：2008-11-04

申请号：US10886926

申请日：2004-07-08

申请人： Jung-Bae Lee ,  Hoe-Ju Chung

发明人： Jung-Bae Lee ,  Hoe-Ju Chung

IPC分类号： G06F13/42

CPC分类号： G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C2207/2254

摘要： A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.

摘要翻译： 存储器系统包括至少一个存储器模块，每个存储器模块具有用于产生模式数据的模式数据产生电路，该模式数据具有共同应用命令信号的多个存储器，并且分别应用相应的数据; 以及存储器控制器，用于分别将命令信号和相应的数据应用于多个存储器，在定时控制操作期间向存储器模块应用模式数据产生命令，使用以下方式计算到达多个存储器中的每一个的数据之间的时间差： 从每个存储器输出的图案数据，并使用计算出的数据到达时间差来接收和输出数据。 因此，在存储器控制器和存储器之间实现稳定的数据传输。

公开(公告)号：US20070271424A1

公开(公告)日：2007-11-22

申请号：US11723821

申请日：2007-03-22

申请人： Jung-Bae Lee ,  Hoe-Ju Chung

发明人： Jung-Bae Lee ,  Hoe-Ju Chung

IPC分类号： G06F12/00

CPC分类号： G06F13/1668

摘要： A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation, transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit and writing the transferred write data at the at least one memory device. An example read operation may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal and an address from the received packet command if the received packet command corresponds to a read operation, transferring the extracted command signal and address to at least one memory device, receiving read data corresponding to the extracted command signal and address from the at least one memory device via write/read data lines internal to the given one memory unit and transmitting the received read data from the interface via read data lines external to the given one memory unit.

摘要翻译： 存储器模块，包括存储器控制器和存储器模块的存储器系统及其方法。 示例性存储器模块可以包括多个存储单元，每个存储器单元具有接口和至少一个存储器件。 示例性写入操作方法可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，提取命令信号，地址和写入数据 如果接收到的分组命令对应于写入操作，则接收到的分组命令，通过给定一个存储器单元内部的写入/读取数据线将提取的写入数据传送到至少一个存储器件，并将传送的写入数据写入至少一个 存储设备。 示例性读取操作可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，从接收到的分组命令中提取命令信号和地址 如果接收的分组命令对应于读取操作，则将所提取的命令信号和地址传送到至少一个存储器件，通过内部的写入/读取数据线从至少一个存储器件接收与所提取的命令信号和地址相对应的读取数据 到给定的一个存储器单元，并且通过给定的一个存储器单元外部的读取数据线从接口发送接收到的读取数据。

公开(公告)号：US07177214B2

公开(公告)日：2007-02-13

申请号：US10991729

申请日：2004-11-18

申请人： Jung-Bae Lee

发明人： Jung-Bae Lee

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C7/12

摘要： Methods for controlling the timing of a pre-charge operation in a memory device are provided. In embodiments of the present invention, the timing may be controlled by dynamically selecting a word line off time based on information about a number of column cycles. This may be accomplished, for example, by routing a word line disable signal via one of a first plurality of delay paths. The methods may further include dynamically selecting a bit line equalization start time based on the information about the number of column cycles. This may be accomplished, for example, by routing a bit line equalization start signal via one of a second plurality of delay paths. Pursuant to still further embodiments of the present invention, systems for controlling timing in a memory device are provided which include a control circuit that is configured to select a word line off time from a plurality of word line off times in response to a word line signal and information about a number of column cycles.

摘要翻译： 提供了用于控制存储器件中的预充电操作的定时的方法。 在本发明的实施例中，可以通过基于关于列周期数的信息来动态地选择字线关闭时间来控制定时。 这可以例如通过经由第一多个延迟路径中的一个来路由字线禁用信号来实现。 所述方法还可以包括基于关于列周期数的信息来动态地选择位线均衡开始时间。 这可以例如通过经由第二多个延迟路径之一路由位线均衡起始信号来实现。 根据本发明的另外的实施例，提供了一种用于控制存储器件中的定时的系统，其包括控制电路，其被配置为响应于字线信号从多个字线关闭时间选择字线关闭时间 以及关于多个列循环的信息。

公开(公告)号：US20050010741A1

公开(公告)日：2005-01-13

申请号：US10886926

申请日：2004-07-08

申请人： Jung-Bae Lee ,  Hoe-Ju Chung

发明人： Jung-Bae Lee ,  Hoe-Ju Chung

IPC分类号： G11C7/00 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22

CPC分类号： G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C2207/2254

摘要： A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.

摘要翻译： 存储器系统包括至少一个存储器模块，每个存储器模块具有用于产生模式数据的模式数据产生电路，该模式数据具有共同应用命令信号的多个存储器，并且分别应用相应的数据; 以及存储器控制器，用于分别将命令信号和相应的数据应用于多个存储器，在定时控制操作期间向存储器模块应用模式数据产生命令，使用以下方式计算到达多个存储器中的每一个的数据之间的时间差： 从每个存储器输出的图案数据，并使用计算出的数据到达时间差来接收和输出数据。 因此，在存储器控制器和存储器之间实现稳定的数据传输。

公开(公告)号：US06806582B2

公开(公告)日：2004-10-19

申请号：US10054700

申请日：2002-01-17

申请人： Mee-Hyun Ahn ,  Jung-Bae Lee

发明人： Mee-Hyun Ahn ,  Jung-Bae Lee

IPC分类号： H01L2348

CPC分类号： H01L23/50 ,  G11C5/025 ,  G11C2207/105 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device comprising control pads and input/output I/O pads capable of reducing the data path for reading and writing data in a cell array, and a method for driving the semiconductor memory device are included. The semiconductor memory device comprises a plurality of memory banks arranged at a cell region of a memory chip, and a plurality of control pads and a plurality of I/O pads, separately arranged from each other at the memory chip, for reading/writing data from/in the memory banks, wherein the plurality of control pads and I/O pads are dispersed at the peripheral region between adjacent memory banks and at the outer portions of the memory banks.

摘要翻译： 一种半导体存储器件，包括能够减少用于在单元阵列中读取和写入数据的数据路径的控制焊盘和输入/输出I / O焊盘，以及用于驱动半导体存储器件的方法。 半导体存储器件包括布置在存储器芯片的单元区域的多个存储器组，以及多个控制焊盘和多个I / O焊盘，这些控制焊盘和多个I / O焊盘在存储芯片处彼此分开布置，用于读/写数据 来自/在存储体中，其中多个控制焊盘和I / O焊盘分散在相邻存储体之间的周边区域和存储体的外部。