公开(公告)号：US07973372B2

公开(公告)日：2011-07-05

申请号：US12382972

申请日：2009-03-27

Applicant: Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

Inventor： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/66659

Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is defined with dopant of higher atomic weight than the lateral extension of the drain.

Abstract translation: 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括与主要部分横向连续并在栅电极下方横向延伸的主要部分（240M或242M）和更轻掺杂的侧向延伸部（240E或242E）。 沿着上半导体表面终止通道区域的侧向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源的横向延伸由比排水管的横向延伸更高的原子量的掺杂剂限定。

公开(公告)号：US07972918B1

公开(公告)日：2011-07-05

申请号：US12545014

申请日：2009-08-20

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top of the well. Each well is defined by a corresponding body-material region (108 or 308) of a selected conductivity type. The regions respectively meet overlying zones (104 and 304) of the opposite conductivity type. The concentration of well dopant of the selected conductivity type locally reaches a maximum in each body-material region at a location no more than 10 times deeper below the upper semiconductor surface than the overlying zone's depth, decreases by at least a factor of 10 in moving from the empty-well maximum-concentration location through the overlying zone to the upper surface, and reaches at least one other maximum in moving from the filled-well maximum-concentration location through the other zone to the upper surface.

Abstract translation: 半导体结构设置有（i）在井的顶部附近具有相对少的阱掺杂物的空阱，以及（ii）在阱的顶部附近具有相当好的掺杂剂的填充阱。 每个孔由所选择的导电类型的对应的主体材料区域（108或308）限定。 这些区域分别满足相反导电类型的覆盖区域（104和304）。 所选择的导电类型的阱掺杂剂的浓度在上半导体表面以上的深度比上覆层的深度低10倍的位置在每个主体材料区域局部达到最大值，在移动中减小至少10倍 从空井最大浓度位置通过上覆区域到上表面，并且从填充井最大浓度位置通过另一区域移动到上表面时达到至少另一个最大值。

公开(公告)号：US07838930B1

公开(公告)日：2010-11-23

申请号：US11977213

申请日：2007-10-23

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/02

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (500, 510, 530, or 540) has a hypoabrupt step-change vertical dopant profile below one (104 or 564) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 568). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material largely undergoes a step increase by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone.

Abstract translation: 绝缘栅场效应晶体管（500,510,530或540）在其源极/漏极区的一个（104或564）下方具有低于一个（104或564）的垂直掺杂剂轮廓，用于减小沿pn结的寄生电容 该源极/漏极区域和相邻的主体材料（108或568）。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体 - 材料位置时，会大大增加至少10倍，不超过10倍 比上部半导体表面更深于该源/漏区。

公开(公告)号：US20100244149A1

公开(公告)日：2010-09-30

申请号：US12382971

申请日：2009-03-27

Applicant: Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

Inventor： Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Abstract translation: 一组高性能类似极性的绝缘栅场效应晶体管（100,108,112,116,120和124或102,110,114,118,122和126）具有可选择地不同的侧向源 /漏极延伸，光晕口和栅介质厚度，适用于为模拟和/或数字应用提供各种晶体管的半导体制造平台。 每个晶体管具有一对源极/漏极区，栅极介电层和栅电极。 每个源极/漏极区域包括主要部分和更轻掺杂的横向延伸部分。 一个晶体管的一个源极/漏极区域的横向延伸比另一个晶体管的源极/漏极区域之一的横向延伸更深地掺杂或/并且在上部半导体表面之下更深地延伸。

公开(公告)号：US07176530B1

公开(公告)日：2007-02-13

申请号：US10803203

申请日：2004-03-17

Applicant: Constantin Bulucea ,  Philipp Lindorfer

Inventor： Constantin Bulucea ,  Philipp Lindorfer

IPC: H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/26586 ,  H01L27/0883 ,  H01L27/0928 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/665 ,  H01L29/7833

Abstract: A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally of materially greater gate dielectric thickness than the surface-channel IGFET so as to operate across a greater voltage range than the surface-channel IGFET. Alternatively or additionally, the channel-junction IGFET may conduct current through a field-induced surface channel. A p-channel surface-channel IGFET (102 or 162), which is typically of approximately the same gate-dielectric thickness as the n-channel surface-channel IGFET, is preferably combined with the two n-channel IGFETs to produce a complementary-IGFET structure. A further p-channel IGFET (106, 180, 184, or 192), which is typically of approximately the same gate dielectric thickness as the n-channel channel-junction IGFET, is also preferably included. The further p-channel IGFET can be a surface-channel or channel-junction device.

Abstract translation: 半导体技术结合了正常n沟道沟道结绝缘栅场效应晶体管（“IGFET”）（104）和n沟道表面沟道IGFET（100或160），以降低低频1 / f 噪声。 沟道结IGFET通常具有比表面沟道IGFET大得多的栅介质厚度，以便在比表面沟道IGFET更大的电压范围内工作。 或者或另外，通道结IGFET可以传导电流通过场诱导的表面通道。 通常与n沟道表面沟道IGFET大致相同的栅介质厚度的p沟道表面沟道IGFET（102或162）优选与两个n沟道IGFET组合， IGFET结构。 还优选包括通常具有与n沟道沟道结IGFET大致相同的栅介质厚度的另外的p沟道IGFET（106,180,184或192）。 另外的p沟道IGFET可以是表面沟道或沟道结器件。

公开(公告)号：US06627950B1

公开(公告)日：2003-09-30

申请号：US08851608

申请日：1997-05-05

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L2976

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7811 ,  Y10S148/126

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Abstract translation: 功率MOSFET器件及其制造方法，使用位于沟槽底部下方的成形深体结，使用位于栅极的多边形沟槽来抑制栅极附近的电压击穿，并使用特殊程序 栅极氧化物在各种沟角处的生长。

公开(公告)号：US06576966B1

公开(公告)日：2003-06-10

申请号：US09535434

申请日：2000-03-23

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L2976

CPC classification number: H01L29/66659 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1045 ,  H01L29/7835

Abstract: An asymmetric insulated-gate field-effect transistor (40) is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion (46), which adjoins the drain zone, and a more heavily doped input portion (42), which adjoins the source zone (44). The drain zone contains a main portion (52) and a more lightly doped extension (50) that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone (53) whose doping determines the threshold voltage. The provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa.

Abstract translation: 非对称绝缘栅场效应晶体管（40）配置在不对称轻掺杂漏极结构中，其减轻热载流子效应，并使得源极特性能够与漏极特性去耦合。 晶体管具有形成有与漏极区相邻的输出部分（46）和与源区（44）相邻的更重掺杂的输入部分（42）的多部分通道。 漏区包含与输出通道部分相遇的主要部分（52）和更轻掺杂的延伸部（50）。 漏极延伸部至少与主漏极部分的上半导体表面一样远，以帮助减少热载流子效应。 输入通道部分位于阈值体区（53）中，其掺杂决定了阈值电压。 避免提供轻掺杂的源延伸，从而改善漏极特性不会损害源特性，反之亦然。

公开(公告)号：US5441900A

公开(公告)日：1995-08-15

申请号：US308698

申请日：1994-09-19

Applicant: Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

Inventor： Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

IPC: H01L27/092 ,  H01L21/265

CPC classification number: H01L27/0921 ,  Y10S148/023 ,  Y10S438/904 ,  Y10S438/917

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract translation: 描述了抑制CMOS结构中的闭锁的独特方法。 可以植入在硅中显示中间水平并满足局部作用和电相容性标准的原子物质，以抑制引起闭锁的寄生双极性行为。 通过CMOS结构在有源MOS器件区域之外的临界寄生双极区域可以实现少数载流子寿命的降低。 实现这一目标的一个方法是在源极/漏极掺杂剂被植入之前，使用源极/漏极掩模来局部注入少数载流子寿命衰减器（MCLR）。 这允许MCLR在n沟道晶体管和p沟道晶体管的不同深度或者甚至不同的物种中被引入。 实现这一目标的另一种方法是要求在隔离氧化，栅极氧化或活性阈值植入完成之前，在该过程中非常早地完成覆盖MCLR植入物。

公开(公告)号：US08610207B2

公开(公告)日：2013-12-17

申请号：US13298283

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/8238

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）利用空阱区实现高性能。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US08502273B2

公开(公告)日：2013-08-06

申请号：US12908458

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/778 ,  H01L21/338

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

Abstract: The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.

Abstract translation: 通过在p型Si衬底中形成n阱以直接位于III-NHEMT族金属漏极区的下方，在p型Si衬底上的III-N HEMT组的缓冲击穿显着增加。 n阱形成在击穿期间变得反向偏置的p-n结，从而通过p-n结的反向偏置击穿电压增加缓冲器击穿，并允许衬底接地。 III-N型HEMT的缓冲层也可以注入与p-n结对准的n型和p型掺杂剂，以最小化衬底和缓冲层之间的接合处的任何漏电流。